參數(shù)資料
型號: ATAM893T-TKQ
廠商: Atmel
文件頁數(shù): 77/98頁
文件大小: 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 4,000
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
79
4680C–4BMCU–01/05
ATAM893-D
Combination Mode 9: Bi-phase Demodulation
SSI mode 1:
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Timer 3 mode 11:
Bi-phase demodulation with Timer 3
In the Bi-phase demodulation mode the timer works like in the Manchester demodulation mode.
The difference is that the bits are decoded with the toggle flip-flop. This flip-flop samples the
edge in the middle of the bit-frame and the compare register 1 match event shifts the toggle flip-
flop output into shift register. Before activating the demodulation the timer and the demodulation
stage must be synchronized with the bit-stream. The Bi-phase code timing consists of parts with
the half bit-length and the complete bit-length. The synchronization routine must start the
demodulator after an interval with the complete bit-length.
The counter can be driven by any internal clock source and the output T3O can be used by
Timer 2 in this mode.
Figure 5-58. Bi-phase Demodulation
01
1
01
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Synchronize
Bi-phase demodulation mode
Timer 3
mode
T3EX
Q1 = SI
CM31 = SCI
SR-DATA
0
000
T3I
Reset
Counter 3
10
1
0
1
0
Bit 0
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