參數(shù)資料
型號: ATAM893T-TKQ
廠商: Atmel
文件頁數(shù): 27/98頁
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標準包裝: 4,000
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大小: 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
33
4680C–4BMCU–01/05
ATAM893-D
This timer starts running automatically after any power-on reset! If the watchdog function is not
activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog
timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system
reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it
overflows. The application software has to accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization
routine. There are two watchdog modes, in one mode the watchdog can be switched on and off
by software, in the other mode the watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be pro-
grammed via the watchdog control register (WDC).
Figure 5-8.
Timer 1 Module
Figure 5-9.
Timer 1 and Watchdog
14-bit
Prescaler
CL1
4-bit
Watchdog
MUX
WDCL
T1IM
T1BP
T1MUX
NRST
INT2
T1OUT
T1CS
SYSCL
SUBCL
Q5
Q1 Q2 Q3 Q4
Q6
Q8
Q11
Q14
RES
CL
Decoder
Watchdog
mode control
MUX for interval timer
Decoder
MUX for watchdog timer
T1RM T1C2 T1C1
T1C0
3
2
WDL
WDR WDT1 WDT0
WDC
RES
T1MUX
SUBCL
T1BP T1IM
T1IM=0
T1IM=1
INT2
T1OUT
T1C2
RESET
(NRST)
Watchdog
Divider/8
Divider
RESET
T1C1
Write of the
T1C1 register
CL1
WDCL
Read of the
CWD register
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