參數(shù)資料
型號: ATAM893T-TKQ
廠商: Atmel
文件頁數(shù): 40/98頁
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 4,000
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大小: 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
45
4680C–4BMCU–01/05
ATAM893-D
If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
5.3.2.9
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit
stage of Timer 2. The timer compares the contents of the compare register current counter value
and if it matches it generates an output signal. Depending on the timer mode, this signal is used
to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next
counter stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit com-
pare value. In all other modes, the two compare registers work independently as a 4- and 8-bit
compare register. When assigned to the compare register a compare event will be suppressed.
Table 5-11.
Timer 2 Output Select Bits
Output Mode
T2OS2
T2OS1
T2OS0
Clock Output
11
1
Toggle mode: a Timer 2 compare match toggles
the output flip-flop (M2)
→T2O
21
1
0
Duty cycle burst generator 1: the DCG output
signal (DCG0) is given to the output and gated by
the output flip-flop (M2)
31
0
1
Duty cycle burst generator 2: the DCG output
signal (DCGO) is given to the output and gated by
the SSI internal data output (SO)
41
0
Bi-phase modulator: Timer 2 modulates the SSI
internal data output (SO) to Bi-phase code
50
1
Manchester modulator: Timer 2 modulates the
SSI internal data output (SO) to Manchester code
60
1
0
SSI output: T2O is used directly as SSI internal
data output (SO)
7
0
1
PWM mode: an 8/12-bit PWM mode
80
0
Not allowed
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