參數(shù)資料
型號(hào): ATAM893T-TKQ
廠商: Atmel
文件頁(yè)數(shù): 57/98頁(yè)
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 4,000
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類(lèi)型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
60
4680C–4BMCU–01/05
ATAM893-D
5.3.3.16
Timer 3 Capture Register
The counter content can be read via the capture register. There are two ways to use the capture
register. In modes 1 and 4, it is possible to read the current counter value directly out of the cap-
ture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3
input or a signal from Timer 2 stores the current counter value into the capture register. This
counter value can be read from the capture register.
5.3.3.17
Timer 3 CaPture Register (T3CP) Byte Read
5.3.4
Synchronous Serial Interface (SSI)
5.3.4.1
SSI Features
2- and 3-wire NRZ
2-wire mode (MCL compatible), additional internal 2-wire link for multi-chip
packaging solutions
With Timer 2
– Bi-phase modulation
– Manchester modulation
– Pulse-width demodulation
– Burst modulation
With Timer 3
– Pulse-width modulation (PWM)
– FSK modulation
– Bi-phase demodulation
– Manchester demodulation
– Pulse-width demodulation
– Pulse position Demodulation
Address: 'Beaux — Subaddress: '4'hex
High Nibble
First read cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
Low Nibble
Second read cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
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