參數(shù)資料
型號: ATAM893T-TKQ
廠商: Atmel
文件頁數(shù): 49/98頁
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 4,000
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
53
4680C–4BMCU–01/05
ATAM893-D
Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. The compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register - after that
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can also be used to detect a time-out error and handle it with an interrupt
routine (see section “Combination Mode 8”).
Figure 5-33. Manchester Demodulation
Timer 3 – Mode 11: Bi-phase Demodulation
In the Bi-phase demodulation mode, the timer operates like in Manchester demodulation mode.
The difference is that the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in
the middle of the bit-frame and the compare register 1 match event shifts the toggle flip-flop out-
put into a shift register (see section “Combination Mode 9”).
Figure 5-34. Bi-phase Demodulation
10
11
1
0
1
0
11
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
Synchronize
Manchester demodulation mode
Timer 3
mode
T3EX
SI
SR DATA
T3I
CM31 = SCI
1
001
1
0
01
1
01
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
Synchronize
Biphase demodulation mode
Timer 3
mode
T3EX
Q1 = SI
CM31 = SCI
SR-DATA
00
0
T3I
Reset
Counter 3
1
0101
0
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