ProASICPLUS Flash Family FPGAs 2- 70 v5.9 Synchronous FIFO Read, Pipeline Mode O" />
參數(shù)資料
型號: APA300-BG456
廠商: Microsemi SoC
文件頁數(shù): 158/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 300K 456-PBGA
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 73728
輸入/輸出數(shù): 290
門數(shù): 300000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 456-BBGA
供應商設(shè)備封裝: 456-PBGA(35x35)
ProASICPLUS Flash Family FPGAs
2- 70
v5.9
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-43 Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-66 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
ECBA
New EMPTY access from RCLKS
3.0*
ns
FCBA
FULL
↓ access from RCLKS ↓
3.0*
ns
ECBH, FCBH,
THCBH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS
1.0
ns
Empty/full/thresh are invalid from the end of
hold until the new access is complete
OCA
New DO access from RCLKS
2.0
ns
OCH
Old DO valid from RCLKS
0.75
ns
RDCH
RDB hold from RCLKS
0.5
ns
RDCS
RDB setup to RCLKS
1.0
ns
RPCA
New RPE access from RCLKS
4.0
ns
RPCH
Old RPE valid from RCLKS
1.0
ns
HCBA
EQTH or GETH access from RCLKS
4.5
ns
Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.
RCLK
RPE
RDATA
EMPTY
EQTH, GETH
FULL
Old Data Out
New Valid Data Out
RDB
Cycle Start
Old RPE Out
New RPE Out
tECBH, tFCBH
tRDCH
tRDCS
tOCA
tECBA, tFCBA
tTHCBH
tHCBA
tCMH
tCML
tCCYC
tRPCH
tOCH
tRPCA
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