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參數(shù)資料
| 型號： | AM79C983AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 41/60頁 |
| 文件大小： | 348K |
| 代理商： | AM79C983AKC |
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Am79C983A
41
P R E L I M I N A R Y
the register jumps to the next level automatically. The data
format is as follows:
E
Packet
0 - Empty
1 - Valid
N3-0
VL
DRE
RNT
S
L
A
FCS
Port Number
Very Long Event
Data Rate Error
Runt Packet
Short Event
Long Event
Alignment Error
FCS Error
Source Address. It is read low
order byte to high order byte.
Bytes 2-7
Note:
The FIFO is emptied by reading. If the FIFO is
full, nothing more is recorded in Sample Error Status. If
the FIFO is empty (bit E = 0), there is nothing in the re-
maining 7 bytes; therefore, the next access will be the
first byte of the 8-byte register.
Report Packet Size
Address:
1110 0011
Report Packet Size is a two-byte register. The eleven
least significant bits are used. It sets the length of the
original packet (in octets) that is transmitted over the
Packet Report Port. The LS Byte is accessed first. The
limits are 14 bytes (binary 000000001110) and 1535
bytes (binary 10111111111). If the register is set at
less than 14, 14 bytes of the original packet are trans-
mitted over the Packet Reports Port. If the register is
set at greater than 1535 bytes, all of the original packet
is sent over the Packet Report Port.
STATS Control
Address:
STATS Control is a 1-byte register. It sets the operation
of the Packet Report Port and the RAUI port.
1110 0100
T
0 Packet tagging is disabled
1 Packet tagging is enabled
0 Appending of a new FCS during port tag-
ging is disabled
1 Appending of a new FCS during port tag-
ging is enabled
F
Register Banks 16 through 30: Port Attribute
Registers
Port Attribute registers are accessed by writing the ap-
propriate port number into the C register, followed by
the attribute number. The table below shows the corre-
sponding register bank for each port.
Except for the Last Source Address Register and the
Preferred Source Register, all registers are four bytes
long and read only unless special conditions are met.
The Last Source Address Register and the Preferred
Source Address Register are six bytes long and their
contents can be written and read.
Once the C Register is programmed with a valid port
and attribute number, the corresponding attribute is
transferred to a holding register upon reading the first
byte. Subsequent accesses to the D register access
the value in a least significant to most significant byte
order. During a read, once the last byte is read, the at-
tribute value is re-transferred to the holding register
and the sequence can be restarted.
When writing the Last Source Address Register and the
Preferred Source Register, if the sequence is aborted
prior to the 6th consecutive write cycle, the register value
is not altered. The sequence (read or write) may be
aborted and restarted by programming the C register.
E
0
0
VL
0
DRE
RNT S
0
N3
N2
L
N1
A
N0
FCS
bit 16
bit 23
bit 56
D Port Read/Write
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
bit 63
MSB
LSB
bit 0
bit 8
bit 15
D Port Read/Write
LSB
Byte 0
Byte 1
bit 7
MSB
0
MSB
T
F
0
0
0
0
0
LSB
D Port Read/Write
Register Bank Access Port
0001 0000 0
0001 0001 1
0001 0010 2
0001 0011 3
0001 0100 4
0001 0101 5
0001 0110 6
0001 0111 7
0001 1000 8
0001 1001 9
0001 1010 10
0001 1011 11
0001 1100 AUI
0001 1101 RAUI
0001 1110 Expansion Bus
(activity recorded
when MACEN
is TRUE)
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