
Am79C983A
39
P R E L I M I N A R Y
Pn/AUI/RAUI/EP
0
Last Source Address Lock
disabled
Last Source Address Lock
enabled
1
Note:
Setting a bit on this register invalidates the cor-
responding Source Address Changes Register.
Register Bank 4: Port Status Registers
These registers are accessed by writing 0000 0100 to
the C register.
Partitioning Status of Ports
Address:
1110 0000
These bits indicate the partition status of the corre-
sponding ports. Ports that are partitioned will transmit
packets. However, the IMR2 device will not repeat
packets received by a partitioned port.
Pn/AUI/RAUI
0
1
Port partitioned
Port connected
Link Test Status of Ports
Address:
1110 0010
The register bits indicate the Link Test Status of the cor-
responding ports. The bit setting is based on data re-
ceived by the QuIET device. Therefore, the bit setting is
invalid if a non-QuIET transceiver is used for the port.
TPn/SPn
0
1
Link Test failed
Link Test passed
Loopback Error Status
Address:
When a packet is transmitted, the DO signal is looped
back to the IMR2 device through the corresponding DI
pins. When a bit on this register is set, data is not being
looped back to the IMR2 device.
1110 0011
Pn/AUI/RAUI
0
1
No Loopback Error
Loopback Error
Note:
The RAUI bit is not valid when the RAUI port is
in the reverse mode.
Receive Polarity Status
Address:
1110 0100
Each register bit represents the receive polarity status
of the corresponding port. The bit setting is based on
data received from the QuIET device through the serial
interface. If another transceiver device is used, the bit
setting reflects what is on the corresponding SDATA.
TPn/SPn
0
1
Polarity correct
Polarity reversed
SQE Test Status
Address:
These register bits reflect the status of the last packet
received from the corresponding port. The RAUI bit is
not valid when the RAUI port is in the reverse mode.
1110 0101
Pn/AUI/RAUI
0
1
No SQE Test Error
SQE Test Error
Register Bank 5: RMON Registers
The RMON registers can be accessed by writing to ad-
dress 0000 0101 and then accessing the individual reg-
isters. The RMON registers are 32-bit counters and
comply with etherStatsEntry of the statistics group of
the RMON MIB (RFC 1757) or etherHistoryEntry of the
History group of RFC 1757. They are 4 bytes long and
are read low order byte to high order byte.
The RMON registers can usually only be read. How-
ever, they can be written to when the Repeater Reset
bit or the Management Reset bit on the Device Config-
uration Register is set.
etherStatsOctets
Address:
The value in this register represents the total number of
octets received (excluding preamble bits, but including
FCS bits) by the IMR2 device.
1110 0000
etherStatsPkts
Address:
The value in this register represents the total number of
packets received by the IMR2 device.
1110 0001
P7
0
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read
Byte 0
Byte 1
MSB
TP7
SP3 SP2 SP1 SP0
TP11
MSB
TP6
TP5
TP4
TP3
TP2
TP10
TP1
TP9 TP8
TP0
Byte 0
Byte 1
D Port Read
LSB
P7
0
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read
Byte 0
Byte 1
MSB
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
TP11 TP
10
TP9 TP8
MSB
Byte 0
Byte 1
D Port Read
LSB
P7
0
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read
Byte 0
Byte 1
MSB