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參數(shù)資料
| 型號： | AM79C983AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 36/60頁 |
| 文件大小： | 348K |
| 代理商： | AM79C983AKC |
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36
Am79C983A
P R E L I M I N A R Y
Multicast Address Pass Enable
Address:
1110 1001
Setting EP disables packet compression on packets
with multicast addresses.
EP
0
Packet compression on pack-
ets with multicast addresses
is enabled
Packet compression on pack-
ets with multicast addresses
is disabled
1
Note:
Zeros should be written to all register bits ex-
cept the EP bit.
Data Rate Mismatch Interrupt Enable
Address:
1110 1010
The IMR2 device can generate an interrupt if received
data is outside the data rate tolerances. Setting a bit
enables the Data Rate Mismatch Interrupt control of
the corresponding port.
Pn/AUI/RAUI/EP
0
Data Rate Mismatch Interrupt
masked (disabled)
Data
Rate
Interrupt enabled
1
Mismatch
Last Source Address Compare Enable
Address:
1110 1100
Setting the EP bit in this register enables a comparison
of the destination address of an incoming packet to the
Last Source Address Register for the expansion port.
Packet compression is disabled when the destination
address matches the Last Source Address Register.
EP
0
Last Source Address Com-
pare masked (disabled)
Last
Source
Compare enabled
1
Address
Note:
Zeros should be written to all register bits except
the EP bit.
Preferred Address Compare Enable
Address:
1110 1111
Setting the EP bit in this register enables a comparison
of the destination address of an incoming packet to the
Preferred Address Register for the expansion port.
Packet compression is disabled when the destination
address matches the Preferred Address Register.
EP
0
Preferred
Compare disabled
Preferred
Compare enabled
Source
Address
1
Source
Address
Note:
Zeros should be written to all register bits except
the EP bit.
Transceiver Interface Changed Interrupt Enable
Address:
1111 0000
When a bit is set, an interrupt is generated if the device
connected to the corresponding port changes from a
QuIET device to a non-QuIET device or from a non-
QuIET device to a QuIET device.
Transceiver 0
PAUI [3:0]
Transceiver 1
PAUI [7:4]
Transceiver 2
Transceiver 3
0
PAUI [11:8]
AUI and RAUI ports
Connection
masked (disabled)
Device Connection Changed Test enabled
Jabber Interrupt Enable
Address:
1111 0001
When a bit in this register is set, an indication of jabber
from a port will cause an interrupt.
D Port Read/Write
Qn
Device
Changed
Test
1
TPn/SPn
0 Jabber Interrupt
masked (disabled)
1 Jabber Interrupt enabled
0
0
0
EP
0
0
0
0
0
0
0
0
0
0
0
0
LSB
D Port Read/Write
Byte 0
Byte 1
MSB
P7
0
MSB
P6
EP
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
0
0
MSB
0
EP
0
0
0
0
0
0
0
0
0
0
0
0
LSB
D Port Read/Write
Byte 0
Byte 1
0
0
0
EP
0
0
0
0
0
0
0
0
0
0
0
0
LSB
D Port Read/Write
Byte 0
Byte 1
MSB
X
MSB
X
X
X
Q3
Q2
Q1
Q0
LSB
D Port Read/Write
TP7
SP3 SP2 SP1 SP0
TP11 TP
10
TP9 TP8
MSB
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Byte 0
Byte 1
LSB
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C983AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Integrated Multiport Repeater 2 (IMR2⑩) |
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