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參數(shù)資料
| 型號： | AM79C983AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AM79C983AKC |
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Am79C983A
37
P R E L I M I N A R Y
Register Bank 3: Port Control Registers
These registers are accessed by writing the bit pattern
0000 0011 into the C register. All registers can be read
from as well as written to.
Alternative Reconnection Algorithm Enable
Address:
1110 0000
The AUI Partitioning/Reconnection state machine can
be programmed for the alternative reconnection algo-
rithm (transmit only). On reset, this register defaults to
the standard reconnection algorithm.
Pn/AUI/RAUI
0
1
Standard Reconnection Algorithm
Alternative Reconnection Algorithm
Link Test Enable
Address
Setting a bit in this register enables the Link Test func-
tion for the corresponding port. This is only in effect
when the IMR2 device is interfaced to a QuIET device.
On reset, this register defaults to Link Test Enabled.
1110 0010
TPn/SPn
0 Link Test Function disabled
1 Link Test Function enabled
Link Pulse Transmit Enable
Address:
1110 0011
Setting a bit in this register enables the corresponding port
to transmit a Link Test Pulse. This is only in effect when the
IMR2 device is interfaced to a QuIET device. On reset, this
register defaults to Link Test Pulse Transmit enabled.
TPn/SPn
0
1
Link Test Pulse Transmit disabled
Link Test Pulse Transmit enabled
Automatic Receiver Polarity Reversal Enable
Address
1110 0100
Setting a bit in this register enables the QuIET device to
automatically invert the receive signal following detec-
tion of the first packet with inverted polarity. This is done
once after reset or link fail. On reset, this register de-
faults to Automatic Receiver Polarity Reversal disabled.
TPn/SPn
0
Automatic Receiver Polarity
Reversal disabled
Automatic Receiver Polarity
Reversal enabled
1
SQE Mask Enable
Address:
Setting a bit in this register allows the corresponding
port to ignore activity on CI during the SQE test window
following a transmission on that port. The SQE test win-
dow is defined by ANSI/IEEE 802.3, Section 7.2.2.2.4
as 6-bit times to 31-bit times following the end of the
packet. Note that the SQE Mask does not affect report-
ing SQE tests on the SQE Status Register and the
SQE Test Change Interrupt Register. On reset, this reg-
ister defaults to SQE Test Mask disabled.
1110 0101
Pn/AUI/RAUI
0
1
SQE Test Mask disabled
SQE Test Mask enabled
Port Enable/Disable
Address 1110 0110
Setting a bit in this register enables the corresponding
port. On reset, the ports default to enabled.
Pn/AUI/RAUI
0
1
Disable the corresponding port
Enable the corresponding port
Setting the EP bit will not disable the expansion bus.
However, if the EP bit is not set, data carried on the ex-
pansion bus that is addressed to a MAC will not be
counted in the MIB attributes.
Port Switching Control
Address:
Setting a bit in this register isolates the corresponding
port. All input signals to the corresponding port and all
information concerning port activity from the transceiver
1110 0111
P7
0
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
MSB
TP7 TP6
TP5
SP3 SP2 SP1 SP0
TP11 TP
10
TP9 TP8
MSB
TP4
TP3
TP2
TP1
TP0
Byte 0
Byte 1
D Port Read/Write
LSB
TP7
SP3 SP2 SP1 SP0
TP11 TP
10
TP9 TP8
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Byte 0
Byte 1
D Port Read/Write
TP7
SP3 SP2 SP1 SP0
TP11 TP
10
TP9 TP8
MSB
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Byte 0
Byte 1
D Port Read/Write
LSB
P7
0
MSB
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
P7
0
MSB
P6
EP
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C983AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Integrated Multiport Repeater 2 (IMR2⑩) |
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