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參數(shù)資料
| 型號： | AM79C983AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 35/60頁 |
| 文件大小： | 348K |
| 代理商： | AM79C983AKC |
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Am79C983A
35
P R E L I M I N A R Y
Pn/AUI/RAUI/EP
0
Runts with Valid FCS Interrupt
masked (disabled)
Runts
with
Interrupt enabled
1
Valid
FCS
Link Status Change Interrupt Enable
Address:
1110 0010
Setting any of the bits in this register causes the INT pin
to be driven when there is a change in the Link Test
state of the corresponding port. The corresponding sta-
tus bit in the Link Test State Change Register is set to 1.
TPn/SPn
0
Link Status Change Interrupt
masked (disabled)
Link Status Change Interrupt
enabled
1
Loopback Error Change Interrupt Enable
Address:
1110 0011
Setting a bit in this register causes an interrupt to be
generated when the IMR2 device senses a change in the
Loop Back Error condition on the corresponding port.
Pn/AUI/RAUI
0
Loopback Error Change Interrupt
masked (disabled)
1 Loopback
Interrupt enabled
Polarity Change Interrupt Enable
Address:
1110 0100
Setting a bit in this register causes an interrupt to be gener-
ated when the polarity of the connected port is changed.
Error
Change
TPn/SPn
0
Polarity
masked (disabled)
Polarity Change Interrupt
enabled
Change
Interrupt
1
SQE Test Error Change Interrupt Enable
Address:
1110 0101
Setting a bit in this register causes an interrupt to be
generated when the IMR2 device senses a change in
the SQE Test Error condition at a port. This occurs
when an attached MAU has SQE Test enabled. A new
interrupt is generated when a condition change is
sensed by the IMR2 device.
Pn/AUI/RAUI
0
SQE
Interrupt masked (disabled)
SQE
Test
Interrupt enabled
Test
Error
Change
1
Error
Change
Source Address Changed Interrupt Enable
Address:
1110 0110
This register enables interrupts caused by a mismatch
between the source address of an incoming packet and
either the Last Source Address Register or the Preferred
Source Address Register. If Last Source Address Lock
is not set and the packet is a valid packet, a mismatch
between the source address and the Last Source
Address Register also causes the new source address
to be written into the Last Source Address Register.
Pn/AUI/RAUI/EP
0
Source
Interrupt masked (disabled)
Source
Address
Interrupt enabled
Address
Changed
1
Changed
Intruder Interrupt Enable
Address:
1110 0111
This register enables interrupts to be generated when the
source address of an incoming packet does not match the
Preferred Source Address Register on the corresponding
port. The corresponding interrupt can be interpreted as
an attempt by an intruder to gain access to the network.
The management system can then take appropriate ac-
tion, such as disabling the corresponding port.
Pn/AUI/RAUI
0
1
Intruder Interrupt masked (disabled)
Intruder Interrupt enabled
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
TP11
TP10
TP9 TP8
MSB
Byte 0
Byte 1
D Port Read/Write
LSB
P7
0
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
MSB
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
TP11 TP
10
TP9 TP8
Byte 0
Byte 1
D Port Read
MSB
LSB
P7
0
MSB
P6
0
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
P7
0
MSB
P6
EP
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
P7
0
P6
EP
P5
RAUI
AUI
P4
P3
P11 P10 P9
P2
P1
P0
P8
LSB
D Port Read/Write
Byte 0
Byte 1
MSB
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C983AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Integrated Multiport Repeater 2 (IMR2⑩) |
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| AM79C983SKC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
| AM79C984 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:enhanced Integrated Multiport Repeater (eIMR⑩) |
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