
62
Am79C976
8/01/00
P R E L I M I N A R Y
I
I
To permit the queuing and de-queuing of message
buffers, ownership of each buffer is allocated to either
the Am79C976 controller or the host. The OWN bit
within the descriptor status information, either TMD or
RMD, is used for this purpose.
Setting the OWN to 1 signifies that the Am79C976 con-
troller currently has ownership of this ring descriptor
and its associated buffer. Only the owner is permitted
to relinquish ownership or to write to any field in the de-
scriptor entry. A device that is not the current owner of
a descriptor entry cannot assume ownership or change
any field in the entry. A device may, however, read from
a descriptor that it does not currently own. Software
should always read descriptor entries in sequential or-
der. When software finds that the current descriptor is
owned by the Am79C976 controller, then the software
must not read ahead to the next descriptor. The soft-
ware should wait at a descriptor it does not own until
the Am79C976 controller sets OWN to 0 to release
ownership to the software. (When LAPPEN (CSR3, bit
5) is set to 1, this rule is modified. See the LAPPEN de-
scription.
At initialization, the base address of the receive de-
scriptor ring is written to CSR24 (lower 16 bits) and
CSR25 (upper 16 bits), and the base address of the
transmit descriptor ring is written to CSR30 and
CSR31.
Figure 28 illustrates the relationship between the initial-
ization base address, the initialization block, the re-
ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is cleared to 0.
1,-8#
Initialization
Block
MOD
PADR[15:0]
PADR[31:16]
PADR[47:32]
LADRF[15:0]
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
RDRA[15:0]
RES
IADR[15:0]
IADR[31:16]
CSR1
CSR2
TDRA[15:0]
RES
RLE
RDRA[23:16]
TLE
TDRA[23:16]
Rcv
Buffers
RMDO
RMD1 RMD2
RMD3
Rcv Descriptor
Ring
N
N
N
N
1st
desc.
2nd
desc.
RMD0
Xmt
Buffers
TMD0
TMD1
TMD2
TMD3
Xmt Descriptor
Ring
M
M
M
M
1st
desc.
2nd
desc.
TMD0
Data
Buffer
N
Data
Buffer
1
Data
Buffer
2
Data
Buffer
M
Data
Buffer
1
Data
Buffer
2