- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C976KIW (ADVANCED MICRO DEVICES INC) PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C976KIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 61/309頁(yè) |
| 文件大?。?/td> | 2070K |
| 代理商： | AM79C976KIW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)當(dāng)前第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)
8/01/00
Am79C976
61
P R E L I M I N A R Y
should not mix the CSR5/CSR7 method with the CMD0
method.
For compatibility with other PCnet family devices, after
the SPND bit in CSR5 is set, it will read back a one only
after the suspend operation is complete, that is, after
both TX_SUSPENDED and RX_SUSPENDED in
STAT0 have been set. It is recommended that when
software polls this register that a delay be inserted be-
tween polls. Continuous polling will reduce the bus
bandwidth available to the Am79C976 controller and
will delay the completion of the suspend operation.
It is recommended that software use the SPNDINT in-
terrupt to determine when the Am79C976 controller
has suspended after one or more suspend bits have
been set. This results in the least competition for the
PCI bus and thus the shortest time from setting of a
suspend bit until completion of the suspend operation.
Clearing the RUN bit in CMD0 will generate a pulse that
will clear all the suspend command and status bits
(TX_SPND, RX_SPND, TX_FAST_SPND and
RX_FAST_SPND in CMD0, TX_SUSPENDED and
RX_SUSPENDED in STAT0, SPND in CSR5 and DRX
and DTX in CSR15). The RX_SPND or TX_SPND bits
may then be set while RUN is cleared. When RUN is
subsequently set, the suspend bit will remain set and
the corresponding operation (transmit or receive) will
be disabled. Since the suspend bit will be cleared when
RUN is cleared, this must be done each time RUN is
set. Since the suspend bits and RUN are in the same
register (CMD0), the suspend bit may be set at the
same time that RUN is set.
For compatibility with other PCnet family devices, set-
ting the STOP bit in CSR0 will also clear the SPND bit
in CSR5. While STOP is set, the DRX or DTX bits in
CSR15 may be set. When the STRT bit in CSR0 is sub-
sequently set, the corresponding operation will be dis-
abled. Since the bits are all cleared when STOP is set,
CSR15 must be written (either directly or indirectly via
the DMA initialization) each time before STRT is set
again.
The suspend bits in CMD0 and STAT0 are equivalent
but not identical to the suspend bits in CSR5, CSR7
and CSR15. Software should use one set of bits or the
other and not mix them. The SPNDINT bit in INT0 has
no equivalent in the CSR registers, so this bit may be
used to detect the completion of a suspend operation
initiated by the SPND bit in CSR5.
*('#!
Descriptor management is accomplished through mes-
sage descriptor entries organized as ring structures in
memory. There are two descriptor rings, one for trans-
mit and one for receive. Each descriptor describes a
single buffer. A frame may occupy one or more buffers.
If multiple buffers are used, this is referred to as buffer
chaining.
*('
Each descriptor ring must occupy a contiguous area of
memory. During initialization, the user-defined base
address for the transmit and receive descriptor rings,
as well as the number of entries contained in the de-
scriptor rings are set up. The programming of the soft-
ware style (SWSTYLE, BCR20, bits 7-0) affects the
way the descriptor rings and their entries are arranged.
When SWSTYLE is at its default value of 0, the de-
scriptor rings are backwards compatible with the
Am79C90 C-LANCE and the Am79C96x PCnet-ISA
family. The descriptor ring base addresses must be
aligned to 8-byte boundaries. Each ring entry contains
a subset of the three 32-bit transmit or receive mes-
sage descriptors that are organized as four 16-bit
structures (SSIZE32 (BCR20, bit 8) is set to 0). Note
that even though the Am79C976 controller treats the
descriptor entries as 16-bit structures, it will always
perform 32-bit bus transfers to access the descriptor
entries. The value of CSR2, bits 15-8, is used as the
upper 8-bits for all memory addresses during bus mas-
ter transfers.
When SWSTYLE is set to 2, 3, or 4, the descriptor ring
base addresses must be aligned to 16-byte bound-
aries. Each ring entry is organized as three 32-bit mes-
sage descriptors (SSIZE32 (BCR20, bit 8) is set to 1).
The fourth DWord is reserved for user software pur-
poses. When SWSTYLE is set to 3, 4, or 5, the order of
the message descriptors is optimized to allow read and
write access in burst mode.
When SWSTYLE is set to 5, the descriptor ring base
addresses must be aligned to a 32-byte boundary.
Each ring entry is organized as eight 32-bit message
descriptors (SSIZE32 (BCR20, bit 8) is set to 1).
Descriptor ring lengths can be set up either by writing
directly to the transmit and receive ring length registers
(CSR76, CSR78) or by using the initialization block. If
the initialization block is used to set up ring lengths, the
ring lengths are restricted to powers of two that are less
than or equal to 128 if SWSTYLE is 0 or 512 if SW-
STYLE is 2 or 3. However, ring lengths of any size up
to 65535 descriptors can be set up by writing directly to
the transmit and receive ring length registers.
The initialization block can not be used if SWSTYLE is
4 or 5. The descriptor ring lengths must be initialized by
writing directly to the appropriate registers.
Each ring entry contains the following information:
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C976KCW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C978AKCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AVCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。