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參數(shù)資料
| 型號(hào)： | AM79C976KIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 143/309頁(yè) |
| 文件大?。?/td> | 2070K |
| 代理商： | AM79C976KIW |
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8/01/00
Am79C976
143
P R E L I M I N A R Y
CTRL2: Control2 Register
Offset 070h
This register contains several miscellaneous control
bits. Each byte of this register controls a single func-
tion. It is not necessary to do a read-modify-write oper-
ation to change a function
’
s settings if only a single byte
of the register is written.
All bits in this register are set to their default values by
H_RESET. All bits are also set to their default values
before EEPROM data are loaded or after an EEPROM
read failure.
The default value for all bits except for bits 2:0 (APDW)
is 0. The default value for the APDW field is 100b.
Table 48.
CTRL2: Control2 Register
Bit
Name
Description
31-19
RES
Reserved locations. Written as zeros and read as undefined.
18-16
FS
Force Speed. This three-bit field sets the MAC
’
s internal speed indicator according to the table
below. The speed indication is used only for LEDs.
15-10
RES
Reserved locations. Written as zeros and read as undefined.
9-8
FMDC
Fast Management Data Clock. When FMDC is set to 2h the MII Management Data Clock will run
at 10 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant and setting
this bit should be used with care. The accompanying external PHY must also be able to accept
management frames at the new clock rate. When FMDC is set to 1h, the MII Management Data
Clock will run at 5 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant
and setting this bit should be used with care. The accompanying external PHY must also be able
to accept management frames at the new clock rate. When FMDC is set to 0h, the MII Management
Data Clock will run at 2.5 MHz max and will be fully compliant to IEEE 802.3u standards.
This field is an alias of BCR32, bits13:12
7
RES
Reserved location. Written as zero and read as undefined.
6
XPHYRST
External PHY Reset. When XPHYRST is set, the Am79C976 controller after an H_RESET or
S_RESET will issue an MII management frame that will reset the external PHY. This bit is needed
when there is no way to guarantee the state of the external PHY. This bit must be reprogrammed
after every H_RESET.
XPHYRST is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 6.
5
XPHYANE
External PHY Auto-Negotiation Enable. This bit will force the external PHY into enabling Auto-
Negotiation. When set to 0 the Am79C976 controller will send an MII management frame disabling
Auto-Negotiation.
XPHYANE is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 5.
4
XPHYFD
External PHY Full Duplex. When set, this bit will force the external PHY into full duplex when Auto-
Negotiation is not enabled.
XPHYFD is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 4.
FS[2:0]
Speed
000
Speed determined by PHY
001
Reserved
010
10 Mb/s
011
100 Mb/s
1XX
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C976KCW | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C978AKCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AVCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C978 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
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