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參數(shù)資料
| 型號(hào)： | AM79C32AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 80/101頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | AM79C32AVC |
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80
Am79C30A/32A Data Sheet
Microprocessor Read/Write Timing
Microprocessor Read Timing
Microprocessor Write Timing
Notes:
1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a
read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of
450 ns.
2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (t
RLRH
+ t
RHRL
) of 480 ns.
3. Read access time is measured from the falling edge of CS or the falling edge of RD, whichever occurs last.
4. CS may go Low before either RD or WR goes Low.
5. In minimal systems, CS may be tied Low.
6. Read and write indirect register operations cannot be mixed without at least one write command register operation between
them.
7. CS may go High before either RD or WR goes High.
8. If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns.
9. RD and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both
CS and RD or WR are Low simultaneously.
Parameter Symbol
Parameter Description
Min
Max
Units
t
RLRH
t
RHRL
t
AVRL
t
AHRH
t
RHCH
t
RACC
t
RHDZ
t
RDCS
RD Pulse Width
200
ns
Read Recovery Time (Notes 1, 2)
200
ns
Address Valid to RD Low
20
ns
Address Hold After RD High
10
ns
RD High to CS High (Note 7)
0
ns
Read Access Time (Note 3)
80
ns
RD High to Data Hi-Z
50
ns
RD Low to CS Low (Note 4)
30
ns
Parameter Symbol
Parameter Description
Min
Max
Units
t
WLWH
t
WHWL
t
AVWL
t
AHWH
t
WHCH
t
DSWH
t
DHWH
t
WRCS
WR Pulse Width
200
ns
Write Recovery Time (Note 1)
200
ns
Address Valid to WR Low
20
ns
Address Hold After WR High (Note 8)
10
ns
WR High to CS High (Note 7)
0
ns
Data Setup to WR High
100
ns
Data Hold After WR High
10
ns
WR Low to CS Low (Note 4)
30
ns
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