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參數(shù)資料
| 型號： | AM79C32AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 36/101頁 |
| 文件大小： | 1607K |
| 代理商： | AM79C32AVC |
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36
Am79C30A/32A Data Sheet
Data Link Controller (DLC)
Overview
A 16-Kbit/s D-channel is time-multiplexed within the
frame structure of the S Interface. The data carried by
the D channel is encoded using the Link Access Proto-
col D-channel (LAPD) format shown in Figure 4. The D
channel can be used to carry either end-to-end signal-
ing or low-speed packet data. Further information con-
cerning LAPD protocol can be found in the CCITT
recommendations. The LIU controls the multiplexing
and demultiplexing of the D-channel data between the
S Interface and the DLC.
The DLC performs processing of Level-1 and partial
Level-2 LAPD protocol, including flag detection and
generation, zero deletion and insertion, Frame Check
Sequence (FCS) processing for error detection, and
some addressing capability. High level protocol pro-
cessing is done by the external microprocessor. The
microprocessor may process the address field in the
LAPD frame depending on the programmed state of
the DLC. The status of the DLC is held in the status reg-
isters and relevant interrupts are generated under user
program control. In addition to transmit and receive
data FIFOs, the DLC contains a 16-bit pseudo-random
number generator (RNG) used in the CCITT D-channel
address allocation procedure.
D-channel Processing
Random Number Generator (RNG)
The RNG is accessible by the microprocessor and op-
erates in the following manner.
On the Low-to-High transition of the reset signal, the
RNG is cleared, then started. The RNG stops when the
LSB or MSB of the 16-bit counter is read by the micro-
processor, or when the MSB is loaded by the micropro-
cessor. Writing to the MSB of the counter loads this
byte but does not start the RNG. The RNG starts when
the LSB of the counter is loaded by the microprocessor.
Frame Abort
The DLC aborts an incoming D-channel frame when
seven contiguous logical 1s are received. When this
occurs, an End-of-Receive-Packet interrupt is issued to
the processor. DER bit 0 is set to a logical 1 when the
last byte of the aborted packet is read from the D-chan-
nel Receive buffer. The Receive-Abort interrupt can be
masked by setting DMR2 bit 0 to a logical 0. With the
exception of the Packet-Reception-in-Progress bit, no
other bits associated with packet reception are updated
after a receive packet abort. The receive frame can be
aborted at any time by setting INIT bit 6 to logical 1.
Similarly, the transmit frame can be aborted by setting
INIT bit 7 to a logical 1. When the transmit frame is
aborted, seven consecutive 1s are transmitted on the S
Interface followed by a logical 0, and DSR1 bit 7 is set
to a logical 1. Seven consecutive 1s followed by a 0 will
continue to be transmitted as long as INIT bit 7 is set to
1. DSR1 bit 7 will be set after each sequence of seven
consecutive 1s followed by 0.
Level-2 Frame Structure
The D-channel Level-2 frame structure conforms to
one of the formats shown in Figure 4. All frames start
and end with the flag sequence consisting of one 0 fol-
lowed by six 1s followed by one 0. A packet consists of
a Level-2 frame minus the flag bytes. The LSB is trans-
mitted first for all bytes except the FCS.
The flag preceding a packet is defined as the opening
flag. Therefore, the byte following an opening flag, by
definition, cannot be an abort or another flag. A closing
flag is defined as a flag that terminates a packet. This
flag can be followed by another flag(s), interframe fill
consisting of all 1s or flags, or the address field of the
next packet. In the latter case, the closing flag of one
packet is the opening flag of the next packet. The DLC
receiver can recognize interframe fill consisting of logi-
cal 1s or flags. The DLC transmitter follows the closing
flag with interframe fill consisting of all 1s (mark Idle) if
DMR4 bit 4 is set to a logical 0, or all 0s (flag Idle) if
DMR4 bit 4 is set to a logical 1. CCITT I-series D-chan-
nel access protocol specifies use of mark Idle.
When a collision is detected (mismatch of a D and E
bit), a complete frame must be retransmitted. For trans-
fer across the S Interface, the S-Interface frame struc-
ture is impressed upon the D-channel frame structure
(LAPD).
Zero Insertion/Deletion
When transmitting, the DLC examines the frame con-
tent between the opening and closing flags. To ensure
24
92
C9
64
B2
D9
EC
76
827.6
813.6
800.0
786.9
774.2
761.9
150.0
738.5
45
22
11
0-8
84
C2
61
B0
393.4
390.2
387.1
384.0
381.0
378.0
375.0
372.1
9B
CD
E6
F3
79
BC
DE
EF
258.1
256.7
255.3
254.0
252.6
251.3
250.0
248.7
E4
F2
F9
FC
FE
FF
192.0
191.2
190.5
189.7
189.0
188.2
Table 37.
Frequencies for Secondary Tone Ringer (Continued)
Counter
Value
(Hz)
Counter
Value
Frequency
(Hz)
Frequency
Counter
Value
Frequency
(Hz)
Counter
Value
Frequency
(Hz)
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