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參數(shù)資料

型號(hào)：	AM79C32AVC
廠商：	ADVANCED MICRO DEVICES INC
元件分類：	數(shù)字傳輸電路
英文描述：	Digital Subscriber Controller⑩ (DSC⑩) Circuit
中文描述：	DATACOM, DIGITAL SLIC, PQFP44
封裝：	PLASTIC, TQFP-44
文件頁數(shù)：	43/101頁
文件大?。?/td>	1607K
代理商：	AM79C32AVC

Am79C30A/32A Data Sheet

D-Channel Mode Register 2 — (DMR2) — Read/Write

Address = Indirect 87H

DMR2 is used to enable/disable the interrupts generated in the DER (see DER definition on page 41). DMR2 is con-

trolled by the microprocessor and does not generate interrupts. DMR2 is defined in Table 40.

Table 40.

D-Channel Mode Register 2

D-Channel Mode Register 3 — (DMR3) — Read/Write

Address = Indirect 8EH

Bit

Logical 1

Logical 0 (Default Value)

Enable Receive Abort interrupt (see DER bit 0)

Disable interrupt

Enable Non-integer Number of Bytes Received interrupt (see DER bit 1)

Disable interrupt

Enable Collision Abort Detected interrupt (see DER bit 2)

Disable interrupt

Enable FCS Error interrupt (see DER bit 3)

Disable interrupt

Enable Overflow Error interrupt (see DER bit 4)

Disable interrupt

Enable Underflow Error interrupt (see DER bit 5)

Disable interrupt

Enable Overrun Error interrupt (see DER bit 6)

Disable interrupt

Enable Underrun Error interrupt (see DER bit 7)

Disable interrupt

Table 41.

D-Channel Mode Register 3

Bit

Logical 1

Logical 0 (Default Value)

Enable Valid Address/End of Address interrupt (default value) (see DSR1 bit 0) Disable interrupt

Enable End of Valid Transmit Packet interrupt (default value) (see DSR1 bit 6) Disable interrupt

Enable Last Byte of Received Packet interrupt (see DSR2 bit 0)