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參數(shù)資料
| 型號： | AM79C30AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 60/101頁 |
| 文件大小： | 1607K |
| 代理商： | AM79C30AVC |
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60
Am79C30A/32A Data Sheet
Peripheral Port Registers
The PP contains the following registers:
Peripheral Port Control Register 1 (PPCR1) Default = 01 Hex
Address = Indirect C0 Hex, Read/Write
Registers
# of Registers
Mnemonic
Peripheral Port Control Register
3
PPCR1, PPCR2, PPCR 3
Peripheral Port Status Register
1
PPSR
Peripheral Port Interrupt Enable Register
1
PPIER
Monitor Transmit Data Register
1
MTDR
Monitor Receive Data Register
1
MRDR
C/I Transmit Data Register
2
CITDR0, CITDR1
C/I Receive Data Register
2
CIRDR0, CIRDR1
7
6
5
4
3
2
1
0
MONTR
ABORT
RQST
MONTR
ENABL
MONTR
CHANL
SELECT
MONTR
EOM
RQST
IC
CHANL
SELECT
IOM 2
ACTV/
DEACT
PORT
MODE
SELECT
BIT 1
PORT
MODE
SELECT
BIT0
Bit
Function
7
Monitor Channel Abort Request—
This bit is automatically cleared during RESET or manually by software as follows:
to send an ABORT message, software should set this bit, wait at least two frames, then clear the bit.
6
Monitor Channel Enable—
This bit only affects IOM-2 operation. When set, the selected monitor channel is enabled.
When cleared, both monitor channels are disabled. Whenever the monitor channel is disabled, the Monitor Transmit and
Receive Data Register (MTDR, MRDR) are updated to their default states: MTDR = FFH, MRDR = 00H.
5
Monitor Channel Select—
This bit only affects IOM-2 operation. When set, Monitor channel 1 is used (second
subframe). When cleared, Monitor channel 0 is used (first subframe).
4
Monitor End-of-Message Request—
When set, this bit forces the Monitor channel transmitter to send an EOM once all
data written into the Monitor Transmit Data Register has been transmitted. This tells the receiving device that the
message is complete. The bit is cleared by hardware when the EOM is sent by reset or by software.
3
IC Channel Select—
This bit only affects IOM-2 operation. When set, the IC2 time slot is used (sixth octet after the frame
sync). When cleared, the IC1 time slot is used (fifth octet after the frame sync). The unused channel is always placed in
a high-impedance state.
2
IOM-2 Activation/Deactivation Bit—
This bit only affects IOM-2 operation. Note that this bit controls only the starting
and stopping of SCLK, BCL/CH2STRB, SFS, and the state of the SBIN/SBOUT pins; this alone does not constitute
activation or deactivation of the IOM-2 bus. The activation/deactivation procedure involves the exchange of a series of
commands and indications over the C/I channel. This procedure, including a state diagram, is detailed in the IOM-2
specification.
IOM-2 Master mode—This bit is set by software. When deactivated, the master will turn on SCLK, BCL/CH2STRB, and
SFS clocks via software by setting this bit when the SBIN pin is pulled Low, indicating that a downstream device wishes
to communicate over the interface.
The IOM-2 activation/deactivation bit is cleared by software or reset. When cleared, the clocks are stopped, and SBIN is
monitored for the reactivation request from the slave (SBIN held Low). [Reset defaults the Peripheral Port to SBP
operation.]
IOM-2 Slave mode—This bit is set by software to initiate an activation request to the master. When set, the SBIN pin is
driven Low, and held Low until the activation/deactivation bit is cleared by software. In response to SBIN going Low the
master will start SCLK, which generates a timing request interrupt in the DSC circuit. The activation/deactivation bit is
cleared by software in response to this interrupt.
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