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參數(shù)資料
| 型號(hào)： | AM79C30AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁(yè)數(shù)： | 33/101頁(yè) |
| 文件大小： | 1607K |
| 代理商： | AM79C30AVC |
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Am79C30A/32A Data Sheet
33
MAP Mode Register 1 — (MMR1) — Read/Write
Address = Indirect 69H
Note:
*To remove the sidetone path completely, it is necessary to enable the STG function by setting MMR1 bit 6 to 1, and program the
STGR coefficient to 9008 (hex).34
MAP Mode Register 2 — (MMR2) — Read/Write
Address = Indirect 6AH
Note:
For most applications, MMR2 bits 5 and 6 should always be written to logical 0. This enables the 50–60 Hz rejection filter and the
internal offset cancellation circuits to operate normally. They can both be disabled when system or test conditions require the
transmission of DC or low frequency signals.
Table 33.
Map Mode Register 1
Bit
Logical 1
Logical 0 (Default Value)
0
A-Law
μ
-Law
1
GX coefficient loaded from register
GX bypassed; gain = 0 dB
2
GR coefficient loaded from register
GR bypassed; gain = 0 dB
3
GER coefficient loaded from register
GER bypassed; gain = 0 dB
4
X coefficient loaded from register
X bypassed; response = flat
5
R coefficient loaded from register
R bypassed; response = flat
6
Sidetone gain coefficient loaded from register
STG gain = –18 dB*
7
Digital loopback #1 at MAP enabled
Digital loopback #1 at MAP disabled
Table 34.
Map Mode Register 2
Bit
Logical 1
Logical 0 (Default Mode)
0
AINB selected
AINA selected
1
LS1/LS2 selected
EAR1/EAR2 selected
2
DTMF enabled
DTMF disabled
3
Tone generator enabled
Tone generator disabled
4
Tone ringer enabled
Tone ringer disabled
5
High pass filter disabled
High pass filter enabled
6
ADC auto-zero function disabled
ADC auto-zero function enabled
7
Reserved, must be Logical 0
Reserved, must be Logical 0
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