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參數(shù)資料
| 型號(hào)： | AM79C30AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 13/101頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | AM79C30AVC |
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Am79C30A/32A Data Sheet
13
FUNCTIONAL DESCRIPTION
Microprocessor Interface (MPI)
The Am79C30A/32A can be connected to any general
purpose 8-bit microprocessor via the MPI. The MCLK
from the Am79C30A/32A can be used as the clock for
the microprocessor. The MPI is an interrupt-driven in-
terface containing all the circuitry necessary for access
to the internal programmable registers, status regis-
ters, coefficient RAM, and transmit/receive buffers.
MPI External Interface
External connections to the MPI are shown in Table 5.
Direct Registers
Access to the Direct Registers of the Am79C30A/32A
is controlled by the state of the CS, RD, WR, A2, A1,
and A0 input pins, as defined below by Table 6.
Indirect Registers
To read from or write to any of the Indirect Registers, an
indirect address command is first written to the Com-
mand Register (CR). One or more data bytes may then
be transferred to or from the selected register through
the Data Register (DR).
Registers within certain groups can be accessed
quickly by using internal circuitry which automatically
increments the indirect value. In Table 7, the bytes
transferred numbers are the number of bytes which are
read or written to the DR after the CR has been loaded.
Whenever the CR is loaded, any previous commands
are automatically terminated.
Note:
The RD and WR signals must never both be Low under normal operating conditions.
Table 5.
MPI External Interface
Name
Direction
Function
D7–D0
Bidirectional
Data Bus
A2–A0
Inputs
Address Line
RD
Input
Read Enable
WR
Input
Write Enable
CS
Input
Chip Select
RESET
Input
Initialization
INT
Output
Interrupt
Table 6.
Direct Register Access Guide
CS
RD
WR
A2
A1
A0
Register(s) Accessed
Mode
0
1
0
0
0
0
Command Register (CR)
W
0
0
1
0
0
0
Interrupt Register (IR)
R
0
1
0
0
0
1
Data Register (DR)
W
0
0
1
0
0
1
Data Register (DR)
R
0
0
1
0
1
0
D-channel Status Register 1 (DSR1)
R
0
0
1
0
1
1
D-channel Error Register (DER) (2-byte FIFO)
R
0
1
0
1
0
0
D-channel Transmit buffer (DCTB) (8- or 16-byte FIFO)
W
0
0
1
1
0
0
D-channel Receive buffer (DCRB) (8- or 32-byte FIFO)
R
0
1
0
1
0
1
Bb-channel Transmit buffer (BBTB)
W
0
0
1
1
0
1
Bb-channel Receive buffer (BBRB)
R
0
1
0
1
1
0
Bc-channel Transmit buffer (BCTB)
W
0
0
1
1
1
0
Bc-channel Receive buffer (BCRB)
R
0
0
1
1
1
1
D-channel Status Register 2 (DSR2)
R
1
X
X
X
X
X
No access (X = logical 0 or 1)
—
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