
44
Am79C30A/32A Data Sheet
D-Channel Mode Register 4 — (DMR4) — Read/Write
Address = Indirect 8FH
Note:
The receiver and transmitter thresholds can only be changed when the Am79C30A/32A is in Idle mode.
Address Status Register — (ASR) — Read Only
Address = Indirect 91H
Table 43.
Table 42.
D-Channel Mode Register 4
Bit
Control
Function
7
X
6
X
5
X
4
X
3
X
2
X
1
0
0
0
Receiver Threshold
1 byte (EFCR bit 0 = 0)
1 byte (EFCR bit 0 = 1)
2 bytes (EFCR bit 0 = 0)
16 bytes (EFCR bit 0 = 1)
4 bytes (EFCR bit 0 = 0)
24 bytes (EFCR bit 0 = 1)
8 bytes (EFCR bit 0 = 0)
30 bytes (EFCR bit 0 = 1)
1 byte (EFCR bit 0 = 0)
1 byte (EFCR bit 0 = 1)
2 bytes (EFCR bit 0 = 0)
6 bytes (EFCR bit 0 = 1)
4 bytes (EFCR bit 0 = 0)
10 bytes (EFCR bit 0 = 1)
8 bytes (EFCR bit 0 = 0)
14 bytes (EFCR bit 1 = 1)
Mark Idle (default value)
Flag Idle
2-byte (default value)
First Received Byte only
Second Received Byte only
Disable FRAR bit 1 compare (default value)
Enable FRAR bit 1 compare
X
X
X
X
X
X
X
0
1
X
X
X
X
X
1
0
X
X
X
X
X
X
1
1
X
X
X
X
0
0
X
X
Transmitter Threshold
X
X
X
X
0
1
X
X
X
X
X
X
1
0
X
X
X
X
X
X
1
1
X
X
X
X
X
0
1
X
X
X
X
X
X
X
0
1
X
X
0
1
1
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Interframe Fill
Address Recognition
C/R Bit Compare
Address Status Register
Bit
Logical 1
Logical 0 (Default Value)
0
FRAR1/SRAR1 address recognized
No FRAR1/SRAR1 address match
1
FRAR2/SRAR2 address recognized
No FRAR2/SRAR2 address match
2
FRAR3/SRAR3 address recognized
No FRAR3/SRAR3 address match
3
FRAR4/SRAR4 address recognized
No FRAR4/SRAR4 address match
4–7
Reserved
Reserved