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參數(shù)資料
| 型號： | AM79C30AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Controller⑩ (DSC⑩) Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP44 |
| 封裝： | PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 18/101頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | AM79C30AVC |
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18
Am79C30A/32A Data Sheet
LIU Registers
The LIU contains the registers shown in Table 9.
LIU Status Register (LSR), Read Only
Address = Indirect A1H
The LSR format is shown in Table 10.
When the microprocessor reads the LSR, bits 3, 4, 5,
and 7 are cleared. The other bits retain the current sta-
tus of the LIU. bits 0 to 2 are defined such that state F2
(see CCITT I.430 state matrix tables) is coded as 0, F3
as 1, F4 as 2, and so on, where bit 0 is the LSB. The
LIU interrupts the microprocessor via bit 4 of the LSR
when activation has been achieved (that is, when the
LIU moves to state F7 upon receipt of INFO 4). During
reset the LSR is 0.
Even though the LIU Status Register (LSR) is
read-only, no default value upon power-up is given due
to the uncertain state of bit 6 (Hookswitch State). Fol-
lowing RESET, the LIU State is F2 and the HSW bit re-
flects the HSW pin, producing a power-up value of
either 00H or 40H.
LIU D-Channel Priority Register (LPR), Read/Write
The LPR contains the priority level for D-channel ac-
cess. Its default value after reset is 0.
The D-channel access procedure of the Am79C30A/
32A uses the priority level programmed in the LPR. The
priority mechanism defined by the CCITT I-series rec-
ommendations is fully implemented if the LPR is pro-
grammed via the microprocessor to conform to the
priority class of the Layer-2 frame to be transmitted.The
LPR has 16 possible programmable priority levels. The
priority levels are numbered 0–15. Priority Level 0 cor-
responds to counting eight 1s in the echo channel, pri-
ority Level 1 corresponds to counting ten 1s in the echo
channel, priority Level 2 corresponds to counting
twelve 1s, etc. The DSC circuit automatically handles
transitions between the programmed priority level n
and the associated odd value n + 1. The priority is
incremented following a successfully transmitted
packet, and decremented when the higher count has
been satisfied.
The LPR format is shown in Table 11.
Table 9.
LIU Registers
Registers
No./Registers Mnemonic
LIU Status Register
1
LSR
LIU Priority Register
1
LPR
LIU Mode Registers
2
LMR1, LMR2
Multiframe Register
1
MF
Multiframe S-bit/Status
Register
1
MFSB
Multiframe Q-bit buffer
1
MFQB
Table 10.
LIU Status Register
Bit
Logical 1
Generates
Interrupt
0-2 Binary values 000 through 110
represent the LIU activation
circuitry’s current state (F2
through F8, respectively) bit 2 is
MSB
No
3
Change of state to F3
If LMR2 bit 3 = 1
4
Change of state from/to F7
If LMR2 bit 6 = 1
5
Change of state from/to F8
If LMR2 bit 4 = 1
6
HSW state
No
7
HSW change of state
If LMR2 bit 5 = 1
Table 11.
LIU Priority Register
Bits
Description
3, 2, 1, 0
D-channel access priority level bit 0 is LSB
7, 6, 5, 4
Reserved, reads logical 0
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