參數(shù)資料
型號： AM486DX4
廠商： Advanced Micro Devices, Inc.
英文描述： High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時鐘可選32位微處理器)
中文描述： 高性能，時鐘可選，3.3伏，32位微處理器（3.3高性能時鐘可選32位微處理器）
文件頁數(shù)： 9/26頁
文件大?。?/td> 335K
代理商： AM486DX4
AMD
Am486DX4 Microprocessor
9
P R E L I M I N A R Y
BRDY
Burst Ready Input (Active Low; Input)
This input pin performs the same cycle during a burst
cycle that RDY performs during a non-burst cycle. BRDY
indicates that the external system has presented valid
data in response to a read or that the external system
has accepted data in response to write. BRDY is ignored
when the bus is idle and at the end of the first clock in
a bus cycle. BRDY is sampled in the second and sub-
sequent clocks of a burst cycle. The data presented on
the data bus is strobed into the microprocessor when
BRDY is sampled active. If RDY is returned simulta-
neously with BRDY, BRDY is ignored and the burst cycle
is prematurely aborted. BRDY is active Low and is pro-
vided with a small pull-up resistor. BRDY must satisfy
the setup and hold times, t
16
and t
17
.
BREQ
Internal Cycle Pending (Active High; Output)
BREQ indicates that the Am486DX4 microprocessor
has internally generated a bus request. BREQ is gen-
erated whether or not the Am486DX4 microprocessor
is driving the bus. BREQ is active High and is never
floated, except for three-state test mode (see FLUSH).
CLK
Clock (Input)
CLK is a 1X clock providing the fundamental timing for
the bus interface unit and is multiplied in accordance
with the CLKMUL pin to provide the internal frequency
for the Am486DX4 microprocessor. All external timing
parameters are specified with respect to the rising edge
of CLK.
CLKMUL
Clock Multiplier (Input)
The clock multiplier input defines the ratio of internal
core clock frequency to external bus frequency. If sam-
pled Low, the core frequency operates at twice the ex-
ternal bus frequency (speed-double mode). If driven
High or left floating speed-triple mode is selected. CLK-
MUL has an internal pull-up to V
CC
and may be left float-
ing in designs that wish to select speed-triple clock
mode.
D31–D0
Data Lines (Inputs/Outputs)
Lines D7–D0 define the least significant byte and lines
D31–D24 define the most significant byte. These sig-
nals must meet setup and hold times t
22
and t
23
for prop-
er operation on reads. The pins are driven during the
second and subsequent write cycle clocks.
D/C,
M/IO, W/R
Data/Control, Memory/Input/Output, Write/Read
(Active High/Active Low; Output)
These are the primary bus definition signals (in Table
2). These signal are driven valid as the ADS signal is
asserted. The bus definition signals are not driven dur-
ing bus hold and follow the timing of the address bus.
The D/C bus cycle definition pin distinguishes memory
and I/O data cycles (D) from the control cycles (C): in-
terrupt acknowledge, halt, and instruction fetching.
The M/IO bus cycle definition pin distinguishes memory
cycles (M) from input/output cycles (IO).
The W/R bus definition pin distinguishes write cycles
from read cycles.
——————————————————————————————————————————————————————————————
Table 2. Bus Cycle Definition
——————————————————————————————————————————————————————————————
DP3–DP0
Data Parity (Active High; Inputs/Outputs)
Data parity is generated on all write data cycles using
the same timing as the data lines. Even parity informa-
tion must be driven back into the microprocessor on the
data parity pins with the same timing as read informa-
tion. This process ensures that the correct parity check
status is indicated. The signals read on these pins do
not affect program execution. Input signals must meet
setup and hold times, t
22
and t
23
. DP3–DP0 should be
connected to V
CC
through a pull-up resistor in systems
not using parity. DP3–DP0 are active High and are driv-
en during the second and subsequent clocks of write
cycles.
EADS
Valid External Address (Active Low; Input)
This pin indicates a valid external address has been
driven onto the Am486DX4 microprocessor address
pins. This address is used to perform an internal cache
invalidation cycle. EADS is active Low and is provided
with an internal pull-up resistor. EADS must satisfy set-
up and hold times, t
12
and t
13,
for proper operation.
FERR
Floating-Point Error (Active Low; Output)
Driven active when a floating-point error occurs. FERR
is similar to the ERROR pin on a 387 math coprocessor.
M/IO
D/C
W/R
Bus Cycle Initiated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Halt/Special Cycle
I/O Read
I/O Write
Code Read
Reserved
Memory Read
Memory Write
相關(guān)PDF資料
PDF描述
AM49DL320BGB701S 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB701T 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB851S 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGB851T 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
AM49DL320BGT701S 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM486DX4100C16BGI 制造商:AMD 功能描述:*
AM486DX5-133V16BHC 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 133MHz 5V 208-Pin SQFP
AM486DX5-133W16BHC 制造商:Advanced Micro Devices 功能描述:MPU AM486 RISC 32-Bit 0.35um 133MHz 5V 208-Pin SQFP
AM486DXPGA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX PGA - Am486DX PGA Package Temperature Comparisons
AM486DXSQFP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am486DX SQFP - Am486DX SQFP Package Temperature Comparisons
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*