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參數(shù)資料
| 型號(hào)： | AM486DX4 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時(shí)鐘可選32位微處理器) |
| 中文描述： | 高性能，時(shí)鐘可選，3.3伏，32位微處理器（3.3高性能時(shí)鐘可選32位微處理器） |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AM486DX4 |
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AMD
Am486DX4 Microprocessor
11
P R E L I M I N A R Y
PCHK
Parity Status (Active Low; Output)
Parity status is driven on the PCHK pin the clock after
RDY for read operations for data sampled at the end of
the previous clock. A parity error is indicated by PCHK
being Low. Parity status is only checked for enabled
bytes as indicated by the byte enable and bus size sig-
nals. PCHK is valid only in the clock immediately after
read data is returned to the microprocessor. At all other
times PCHK is inactive High. PCHK is never floated ex-
cept during three-state test mode (see FLUSH).
PLOCK
Pseudo-Lock (Active Low; Output)
PLOCK indicates that the current bus transaction re-
quires more than one bus cycle to complete. Examples
of such operations are floating-point long reads and
writes (64 bits), segment table descriptor reads (64 bits),
and cache line fills (128 bits). The Am486DX4 micro-
processor drives PLOCK active until the addresses for
the last bus cycle of the transaction have been driven,
regardless of whether RDY or BRDY has been returned.
Normally PLOCK and BLAST are inverse of each other.
However, during the first bus cycle of a 64-bit floating-
point write, both PLOCK and BLAST will be asserted.
PLOCK
is a function of the BS8, BS16, and KEN inputs.
PLOCK should be sampled only if the clock RDY is re-
turned. PLOCK is active Low and is not driven during
bus hold.
RESET
Reset (Active High; Input)
This pin forces the Am486DX4 microprocessor to begin
execution at a known state. The microprocessor cannot
begin execution of instructions until at least 1 ms after
V
CC
and CLK have reached their proper DC and AC
specifications. The RESET pin should remain active
during this time to ensure proper microprocessor oper-
ation. RESET is active High. RESET is asynchronous
but must meet setup and hold times, t
20
and t
21,
for rec-
ognition in any specific clock.
RDY
Non-Burst Ready (Active Low; Input)
This input pin indicates that the current bus cycle is com-
plete. RDY indicates that the external system has pre-
sented valid data on the data pins in response to a read,
or that the external system has accepted data from the
Am486DX4 microprocessor in response to a write. RDY
is ignored when the bus is idle and at the end of the bus
cycle’s first clock.
RDY is active during address hold. Data can be returned
to the processor while AHOLD is active.
RDY is active Low and is not provided with an internal
pull-up resistor. RDY must satisfy setup and hold times,
t
16
and t
17
,
for proper chip operation.
TCK
Test Clock (Input)
Test Clock is an input to the Am486DX4 CPU and pro-
vides the clocking function required by the JTAG bound-
ary scan feature. TCK is used to clock state information
and data into and out of the component. State select
information and data are clocked into the component on
the rising edge of TCK on TMS and TDI, respectively.
Data is clocked out of the component on the falling edge
of TCK on TDO.
TDI
Test Data Input (Input)
TDI is the serial input used to shift JTAG instructions
and data into the component. TDI is sampled on the
rising edge of TCK, during the SHIFT-IR and the
SHIFT-DR TAP controller states. During all other tap
controller states, TDI is a “don’t care.”
TDO
Test Data Output (Output)
TDO is the serial output used to shift JTAG instructions
and data out of the component. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR
Test Access Port (TAP) controller states. At all other
times, TDO is driven to the high-impedance state.
TMS
Test Mode Select (Input)
TMS is decoded by the JTAG TAP to select the operation
of the test logic. TMS is sampled on the rising edge of
TCK. To guarantee deterministic behavior of the TAP
controller, TMS is provided with an internal pull-up re-
sistor.
UP
Upgrade Present (Active Low; Input)
The Upgrade Present pin forces the Am486DX4 CPU
to three-state all its outputs and enter the power-down
mode. When the Upgrade Present pin is sampled as-
serted by the CPU in the clock before the falling edge
of RESET, the power-down mode is enabled. UP has
no effect on the power-down status except during this
edge. The CPU is also forced to three-state all of its
outputs immediately in response to this signal. The UP
signal must remain asserted in order to keep the pins
three-state. UP is active Low and is provided with an
internal pull-up resistor.
VOLDET
Voltage Detect (Active Low; Output)
The voltage detect signal allows external system logic
to distinguish between a 5-V Am486 processor and the
3.3-V Am486DX4 processor. The signal is active Low
for a 3.3-V Am486DX4 processor.
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