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參數(shù)資料
| 型號： | AM486DX4 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時(shí)鐘可選32位微處理器) |
| 中文描述： | 高性能，時(shí)鐘可選，3.3伏，32位微處理器（3.3高性能時(shí)鐘可選32位微處理器） |
| 文件頁數(shù)： | 18/26頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AM486DX4 |
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AMD
18
Am486DX4 Microprocessor
P R E L I M I N A R Y
Operating Frequency/Bus Frequency: 100/33 MHz
; T
CASE
=0
°
C to +85
°
C; C
L
=50 pF unless otherwise specified.
Note
:
1. Not 100% tested. Guaranteed by design characterization.
Preliminary
Symbol
Parameter Description
Operating Frequency
Notes
Figure
Min
8
Max
33
Unit
MHz
t
1
t
1a
t
2
t
3
t
4
t
5
CLK Period
2
30
125.5
ns
CLK Period Stability
Adjacent Clocks
0.1%
CLK High Time
@ 2.0 V
2
11
ns
CLK Low Time
@ 0.8 V
2
11
ns
CLK Fall Time
2
3
ns
CLK Rise Time
2
3
ns
t
6
A31–A2, PWT, PCD, M/IO, BE3–BE0, D/C,
W/R, ADS, LOCK, FERR, BREQ, HLDA
Valid Delay
A31–A2, PWT, PCD, M/IO, BE3–BE0, D/C,
W/R, ADS, LOCK, FERR, BREQ, HLDA
Float Delay
PCHK Valid Delay
7
3
14
ns
t
7
(Note 1)
8
20
ns
t
8
t
8a
t
9
t
10
6
3
14
ns
BLAST, PLOCK Valid Delay
7
3
14
ns
BLAST, PLOCK
Float Delay
(Note 1)
8
20
ns
D31–D0, DP3–DP0 Write Data Valid Delay
7
3
14
ns
t
11
t
12
t
13
D31–D0, DP3–DP0 Write Data Float Delay
(Note 1)
8
20
ns
EADS Setup Time
4
5
ns
EADS Hold Time
4
3
ns
t
14
KEN, BS16, BS8 Setup Time
4
5
ns
t
15
t
16
t
17
t
18
t
18a
KEN, BS16, BS8 Hold Time
4
3
ns
RDY, BRDY Setup Time
5
5
ns
RDY, BRDY Hold Time
5
3
ns
HOLD, AHOLD Setup Time
4
6
ns
BOFF Setup Time
4
7
ns
t
19
HOLD, AHOLD, BOFF Hold Time
4
3
ns
t
20
RESET, FLUSH, A20M, NMI, INTR, IGNNE
Setup Time
RESET, FLUSH, A20M, NMI, INTR, IGNNE
Hold Time
D31–D0, DP3–DP0, A31–A4 Read Setup
Time
D31–D0, DP3–DP0, A31–A4 Read Hold
Time
3, 4
5
ns
t
21
3, 4
3
ns
t
22
4, 5
5
ns
t
23
4, 5
3
ns
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