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參數(shù)資料
| 型號： | AM486DX4 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時鐘可選32位微處理器) |
| 中文描述： | 高性能，時鐘可選，3.3伏，32位微處理器（3.3高性能時鐘可選32位微處理器） |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AM486DX4 |
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AMD
8
Am486DX4 Microprocessor
P R E L I M I N A R Y
PIN DESCRIPTIONS
The following paragraphs define the Am486DX4 CPU
pins (signals).
A31–A4/A3–A2
Address Lines (Inputs/Outputs)/(Outputs)
A31–A2, together with the byte enables BE3–BE0, de-
fine the physical area of memory or input/output space
accessed. Address lines A31–A4 are used to drive ad-
dresses into the microprocessor to perform cache line
invalidations. Input signals must meet setup and hold
times, t
22
and t
23
. A31–A2 are not driven during bus or
address hold.
A20M
Address Bit 20 Mask (Active Low; Input)
When asserted, the Am486DX4 microprocessor masks
physical address bit 20 (A20) before performing a look-
up to the internal cache or driving a memory cycle on
the bus. A20M emulates the address wraparound at
1 Mbyte, which occurs on the 8086. A20M is active Low
and should be asserted only when the processor is in
Real Mode. This pin is asynchronous but should meet
setup and hold times, t
20
and t
21,
for recognition in any
specific clock. For proper operation, A20M should be
sampled High at the falling edge of RESET.
ADS
Address Status (Active Low; Output)
ADS indicates that a valid bus cycle definition and ad-
dress are available on the cycle definition lines and ad-
dress bus. ADS is driven active in the same clock as the
addresses are driven. ADS is active Low and is not driv-
en during bus hold.
AHOLD
Address Hold (Active High; Input)
This request allows another bus master access to the
Am486DX4 microprocessor’s address bus for a cache
invalidation cycle. The Am486DX4 microprocessor
stops driving its address bus in the clock following
AHOLD going active. Only the address bus is floated
during address hold; the remainder of the bus remains
active. AHOLD is active High and is provided with a
small internal pull-down resistor. For proper operation,
AHOLD must meet setup and hold times, t
18
and t
19
.
BE3–BE0
Byte Enables (Active Low; Outputs)
These pins indicate active bytes during read and write
cycles. During the first cycle of a cache fill, the external
system should assume that all byte enables are active.
BE3 applies to D31–D24, BE2 applies to D23–D16, BE1
applies to D15–D8, and BE0 applies to D7–D0. BE3–
BE0 are active Low and are not driven during bus hold.
The Am486DX4 processor provides four special bus cy-
cles to indicate that certain instructions have been ex-
ecuted, or certain conditions have occurred internally.
The special bus cycles (in Table 1) are defined when the
bus cycle definition pins are in the following state:
M/IO=0, D/C=0, and W/R=1. During these cycles the
address bus is driven Low while the data bus is undefined.
The external hardware must acknowledge these special
bus cycles by returning RDY and BRDY.
——————————————————————————————————————————————————————————————
——————————————————————————————————————————————————————————————
BS8/BS16
Bus Size 8 (Active Low; Input)/
Bus Size 16 (Active Low; Input)
These pins cause the Am486DX4 microprocessor to run
multiple bus cycles to complete a request from devices
that cannot provide or accept 32 bits of data in a single
cycle. The bus sizing pins are sampled every clock. The
state of these pins in the clock before RDY is used by
the Am486DX4 microprocessor to determine the bus
size. These signals are active Low and are provided with
internal pull-up resistors. These inputs must satisfy set-
up and hold times, t
14
and t
15,
for proper operation.
BLAST
Burst Last (Active Low; Output)
BLAST indicates that the next time BRDY is returned,
then the burst bus cycle is complete. BLAST is active
for both burst and non-burst bus cycles. BLAST is active
Low and is not driven during bus hold.
BOFF
Backoff (Active Low; Input)
This input pin forces the Am486DX4 microprocessor to
float its bus in the next clock. The microprocessor floats
all pins normally floated during bus hold, but HLDA is
not asserted in response to BOFF. BOFF has higher
priority than RDY or BRDY; if both are returned in the
same clock, BOFF takes effect. The microprocessor re-
mains in bus hold until BOFF is negated. If a bus cycle
is in progress when BOFF is asserted, the cycle is re-
started. BOFF is active Low and must meet setup and
hold times, t
18a
and t
19,
for proper operation.
Table 1 . Special Bus Cycle Encoding
BE3
1
BE2
1
BE1
1
BE0
0
Special Bus Cycles
Shutdown
1
1
0
1
Flush
1
0
1
1
Halt
0
1
1
1
Write Back
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