
AMD
Am486DX4 Microprocessor
13
P R E L I M I N A R Y
CPU IDENTIFICATION CODES
The DX register always contains a component identifi-
cation at the conclusion of RESET. The upper byte of
DX (DH) contains 04 and the lower byte of DX (DL)
contains a CPU type/stepping identifier.
ARCHITECTURAL OVERVIEW
The Am486DX4 processor is a 32-bit architecture with
on-chip memory management and cache memory
units. It is a fully compatible member of the Am486 Fam-
ily.
On-chip cache memory allows frequently used data and
code to be stored on-chip, thereby reducing accesses
to the external bus. A clock multiplier has been added
to speed up internal operations. RISC design tech-
niques are used to reduce instruction cycle times. A
burst bus feature enables fast cache fills.
The Am486 CPU Memory Management Unit (MMU)
consists of a segmentation unit and a paging unit. Seg-
mentation allows management of the logical address
space by providing easy data and code relocatibility and
efficient sharing of global resources. The paging mech-
anism operates beneath segmentation and is transpar-
ent to the segmentation process. Paging is optional and
can be disabled by system software. Each segment can
be divided into one or more 4-Kbyte segments. To im-
plement a virtual memory system, the Am486DX4 mi-
croprocessor supports full restartability for all page and
segment faults.
Memory is organized into one or more variable length
segments, each up to 4 Gbyte (2
32
bytes) in size. A
segment can have attributes associated with it. These
Table 7. CPU ID
Component ID
(DH)
Component ID
(DL)
04
32
Table 8. JTAG ID Code
Version Code
Part Number
Code
Manufacturer
Identity
00h
0432
01
attributes include its location, size, type (i.e., stack,
code, or data), and protection characteristics. Each task
on an Am486DX4 microprocessor can have a maximum
of 16,381 segments, each up to 4 Gbyte in size. Thus,
each task has a maximum of 64 Tbyte (terabytes) of
virtual memory.
The segmentation unit provides four levels of protection
for isolating and protecting applications and the operat-
ing system from each other. The hardware enforced pro-
tection allows high integrity system designs.
The Am486DX4 microprocessor has three modes of op-
eration: Real Address Mode (Real Mode), Virtual Ad-
dress Mode (Protected Mode), and within Protected
Mode, tasks may be performed in Virtual 8086 Mode.
In Real Mode, the Am486DX4 microprocessor operates
as a very fast 8086. Real Mode is required primarily to
set up the processor for Protected Mode operation. Pro-
tected Mode provides access to the sophisticated mem-
ory management paging and privilege capabilities of the
processor.
Within Protected Mode, software can perform a task
switch to enter into tasks designated as Virtual 8086
Mode tasks. Each Virtual 8086 task behaves with 8086
semantics, allowing 8086 software (an application pro-
gram or an entire operating system) to execute.
The on-chip cache is 8 Kbyte. It is four-way set associa-
tive and follows a write-through policy. The on-chip
cache includes features that provide flexibility in exter-
nal memory system design. Individual pages can be
designated as cacheable or non-cacheable by software
or hardware. The cache can also be enabled and dis-
abled by software or hardware.
Finally, the Am486DX4 microprocessor has features
that facilitate high-performance hardware designs. The
clock multiplier improves execution performance with-
out increasing the board design complexity. This clock
multiplier enhances all operations operating out of the
cache and/or not blocked by external bus assesses. The
burst bus feature enables fast cache fills.