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參數(shù)資料
| 型號(hào)： | AM486DX4 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor(3.3V高性能時(shí)鐘可選32位微處理器) |
| 中文描述： | 高性能，時(shí)鐘可選，3.3伏，32位微處理器（3.3高性能時(shí)鐘可選32位微處理器） |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 335K |
| 代理商： | AM486DX4 |
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AMD
10
Am486DX4 Microprocessor
P R E L I M I N A R Y
FERR is included for compatibility with systems using
DOS-type floating-point error reporting. FERR is active
Low, and is not floated during bus hold, except during
three-state test mode (see FLUSH).
FLUSH
Cache Flush (Active Low; Input)
FLUSH forces the Am486DX4 microprocessor to flush
its entire internal cache. FLUSH is active Low and need
only be asserted for one clock. FLUSH is asynchronous
but setup and hold times, t
20
and t
21,
must be met for
recognition in any specific clock. FLUSH being sampled
Low in the clock before the falling edge of RESET caus-
es the Am486DX4 microprocessor to enter the
three-state test mode.
HLDA
Hold Acknowledge (Active High; Output)
HLDA goes active in response to a hold request pre-
sented on the HOLD pin. HLDA indicates that the
Am486DX4 microprocessor has given the bus to anoth-
er local bus master. HLDA is driven active in the same
clock that the Am486DX4 microprocessor floats its bus.
HLDA is driven inactive when leaving bus hold. HLDA
is active High and remains driven during bus hold. HLDA
is never floated except during three-state test mode (see
FLUSH).
HOLD
Bus Hold Request (Active High; Input)
This input pin allows another bus master complete con-
trol of the Am486DX4 microprocessor bus. In response
to HOLD going active, the Am486DX4 microprocessor
floats most of its output and input/output pins. HLDA is
asserted after completing the current bus cycle, burst
cycle, or sequence of locked cycles. The Am486DX4
microprocessor remains in this state until HOLD is deas-
serted. HOLD is active High and is not provided with an
internal pull-down resistor. HOLD must satisfy setup
and hold times t
18
and t
19
for proper operation.
IGNNE
Ignore Numeric Error (Active Low; Input)
When this pin is asserted, the Am486DX4 microproces-
sor will ignore a numeric error and continue executing
non-control floating-point instructions. When IGNNE is
deasserted, the Am486DX4 microprocessor will freeze
on a non-control floating-point instruction if a previous
floating-point instruction caused an error. IGNNE has
no effect when the NE bit in Control Register 0 is set.
IGNNE is active Low and is provided with a small inter-
nal pull-up resistor. IGNNE is asynchronous but must
meet setup and hold times, t
20
and t
21,
to ensure recog-
nition in any specific clock.
INTR
Maskable Interrupt (Active High; Input)
INTR indicates an external interrupt has been generat-
ed. If the internal interrupt flag is set in EFLAGS, active
interrupt processing is initiated. The Am486DX4 micro-
processor generates two locked interrupt acknowledge
bus cycles in response to the INTR pin going active.
INTR must remain active until the interrupt acknowledg-
es have been performed. This ensures that the interrupt
is recognized. INTR is active High and is not provided
with an internal pull-down resistor. INTR is asynchro-
nous, but must meet setup and hold times, t
20
and t
21,
for recognition in any specific clock.
KEN
Cache Enable (Active Low; Input)
KEN is used to determine whether the current cycle is
cacheable. When the Am486DX4 microprocessor gen-
erates a cacheable cycle and KEN is active, the cycle
becomes a cache line fill cycle. Returning KEN active
one clock before RDY during the last read in the cache
line fill causes the line to be placed in the on-chip cache.
KEN is active Low and is provided with a small internal
pull-up resistor. KEN must satisfy setup and hold times,
t
14
and t
15,
for proper operation. LOCK
Bus Lock (Active Low; Output)
LOCK indicates the current bus cycle is locked. The
Am486DX4 microprocessor does not allow a bus hold
when LOCK is asserted (but address holds are al-
lowed). LOCK goes active in the first clock of the first
locked bus cycle and goes inactive after the last clock
of the last locked bus cycle. The last locked cycle ends
when RDY is returned. LOCK is active Low and is not
driven during bus hold. Locked read cycles are not trans-
formed into cache fill cycles if KEN is active.
NMI
Non-Maskable Interrupt (Active High; Input)
A high NMI signal indicates that external non-maskable
interrupt occurred. NMI is rising edge sensitive, but must
be held Low for at least four-CLK periods before the
rising edge. NMI does not have an internal pull-down
resistor. NMI is asynchronous, but must meet setup and
hold times, t
20
and t
21,
for recognition in any specific
clock.
PCD/PWT
Page Cache Disable/Page Write-Through
(Active High; Outputs)
The outputs reflect the state of the page attribute bits,
PWT and PCD, in the page table or page directory entry.
If paging is disabled or unpaged cycles occur, PWT and
PCD reflect the state of the PWT and PCD bits in Control
Register 3. PWT and PCD have the same timing as the
cycle definition pins (M/IO, D/C, and W/R). PWT and
PCD are active High and are not driven during bus hold.
PCD is masked by the Cache Disable Bit (CD) in Control
Register 0.
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