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| 型號： | AM29BDS323D |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 32兆位（2米× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 43/44頁 |
| 文件大小： | 746K |
| 代理商： | AM29BDS323D |
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Am29BDS323D
43
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (February 15, 2000)
Limited, non-public release.
Revision B (June 20, 2000)
Public release, with the following changes:
Block Diagram
Corrected address range to A0
–
A20.
Ordering Information
Deleted reference to 54 MHz speed option.
Device Bus Operations table
Split address range column into two columns.
AC Characteristics
Asynchronous Read:
In table, changed
“
falling
”
to
“
rising
”
in description of t
AAVDS
. In diagram, modified
t
AAVDS
and t
AAVDH
waveforms to reference from the
rising edge of AVD#.
Synchronous/Burst Read table:
Added t
RDYS
, t
CEH
specifications.
Erase/Program Operations table, Program Operations
Timings figure, Chip/Sector Erase Operations Timings
figure:
Added t
AVDP
. Added PS waveforms to program
operations timings figure.
Initial Access with Power Savings (PS) and
Address Boundary Latency figure
Modified D0 data to extended to D1.
Erase and Programming Performance
Added typical and maximum accelerated chip pro-
gramming time.
Revision B+1 (November 27, 2000)
Accelerated Program Operation, Program
Command Sequence
Added text indicating that setors must be unlocked
prior to raising V
PP
to V
ID
.
Chip Erase Command Sequence
Corrected the command sequence length during
unlock bypass mode from four cycles to two.
DC Characteristics table
Added specification for active burst mode current with
OE# high, I
CCB2
. Original I
CCB
specification is now
named I
CCB1
.
AC Characteristics
Figure 9, Burst Mode Read:
Corrected RDY waveform
to indicate behavior when PS is enabled and when
RDY is in the high impedance state.
Figure 14, Accelerated Unlock Bypass Programming
Timing:
Modified Note 3 to indicate that sectors must
be unlocked prior to raising V
PP
to V
ID
.
Revision B+2 (November 30, 2000)
Figure 10, Asynchronous Mode Read
Corrected endpoint for t
AAVDS
specification.
Figure 16, Toggle Bit Timings
(During Embedded Algorithm)
Corrected OE# waveform during second VA (valid
address) period.
Revision B+3 (December 21, 2000)
Figure 9, Burst Mode Read
Corrected RDY waveform.
Revision B+4 (September 4, 2001)
Global
The 90 ns asynchronous access time has been
changed to 110 ns. Note that the device now has a new
ordering part number and a new package marking.
Sector Erase Command Sequence, DQ7: Data#
Polling, and DQ6: Toggle Bit I
Added explanatory text to indicate 200 μs wait for first
status read occurring in a different bank than the last
sector selected for erasure in a multiple bank sector
erase command sequence.
Table 4, Command Definitions
Added extended autoselect device ID to table (fifth
cycle). Added Note 9.
Figure 18, Initial Access with Power Saving (PS)
Function and Address Boundary Latency
Modified the pulse time RDY is low and in High-Z.
Added note to indicate that RDY exhibits the same
behavior when the burst address begins on an address
boundary without PS enabled.
Figure 19, Initial Access
with Address Boundary Latency
Added figure.
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