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參數(shù)資料
| 型號(hào)： | AM29BDS323D |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 32兆位（2米× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大小： | 746K |
| 代理商： | AM29BDS323D |
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12
Am29BDS323D
P R E L I M I N A R Y
I
When WP# is at V
IL
,
the two outermost sectors are
locked.
I
When V
PP
is at V
IL
, all sectors are locked.
The following hardware data protection measures pre-
vent accidental erasure or programming, which might
otherwise be caused by spurious system level signals
during V
CC
power-up and power-down transitions, or
from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
quent writes are ignored until V
CC
is greater than
V
LKO
. The system must provide the proper signals to
the control inputs to prevent unintentional writes when
V
CC
is greater than V
LKO
.
Write Pulse
“
Glitch
”
Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
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