參數(shù)資料
型號： AM29BDS323D
廠商： Advanced Micro Devices, Inc.
英文描述： 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 32兆位（2米× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存
文件頁數(shù)： 18/44頁
文件大?。?/td> 746K
代理商： AM29BDS323D
18
Am29BDS323D
P R E L I M I N A R Y
erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sec-
tors. The time between these additional cycles must be
less than 50 μs, otherwise erasure may begin. Any
sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written.
Any command other than
Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode.
The
system must rewrite the command sequence and any
additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase
operation is in progress, the system can read data from
the non-erasing bank.
The system can determine the status of the erase oper-
ation by reading DQ7 or DQ6/ DQ2 in the erasing bank.
Note that the host system must wait 200 μs after the
last sector erase command to obtain status information
if the first status read is in a different bank than the last
sector selected for erasure. For example, if sector 0,
which is in bank B, was the last sector selected for era-
sure, and the host system requests its first status read
from sector 71, which is in bank A, then the device
requires 200 μs before status information will be avail-
able. Refer to the Write Operation Status section for
information on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. However, note that a
hardware reset
immediately
terminates the erase operation. If that
occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
The host system may also initiate the sector erase
command sequence while the device is in the unlock
bypass mode. The command sequence is four cycles
cycles in length instead of six cycles.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 13 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the minimum 50 μs
time-out period during the sector erase command se-
quence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded
Program algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a
maximum of 20 μs to suspend the erase operation.
However, when the Erase Suspend command is
written during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The
system can read data from or program data to any
sector not selected for erasure. (The device
“
erase
suspends
”
all sectors selected for erasure.) Reading at
any address within erase-suspended sectors produces
status information on DQ7
–
DQ0. The system can use
DQ7, or DQ6 and DQ2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on
these status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard program operation. Refer to the
Write Operation Status section for more information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Functions and Autoselect Command
Sequence sections for details.
To resume the sector erase operation, the system must
write the Erase Resume command. The bank address
of the erase-suspended bank is required when writing
this command. Further writes of the Resume command
are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
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