參數(shù)資料
型號(hào)： AK5702VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 4-Channel ADC with PLL & MIC-AMP
中文描述： 4通道ADC，帶鎖相環(huán)
文件頁(yè)數(shù)： 56/76頁(yè)
文件大小： 933K
代理商： AK5702VN
[AK5702]
MS0623-E-00
2007/06
- 56 -
DIF1-0: Audio Interface Format (Table 14)
Default: “11” (I
2
S)
BCKP: BCLK/BCLK Polarity at DSP Mode (Table 17)
0: SDTO is output by the rising edge (“
↑
”) of BCLK/BCLK. (default)
1: SDTO is output by the falling edge (“
↓
”) of BCLK/BCLK.
MSBS: LRCK/LRCK Phase at DSP Mode (Table 17)
0: The rising edge (“
↑
”) of LRCK/LRCK is half clock of BCLK/BCLK before the channel change. (default)
1: The rising edge (“
↑
”) of LRCK/LRCK is one clock of BCLK/BCLK before the channel change.
MIXA: ADCA Output Data Select (Table 18)
0: Normal operation (default)
1: (L+R)/2
TDM1-0: TDM Format Select (Table 14, Table 15 Table 16)
Addr
Register Name
D7
D6
05H
fs Select
HPFA1
HPFA0
Default
0
0
FS3-0: Sampling Frequency Select (Table 5 and Table 6) and MCKI Frequency Select (Table 11)
Default: “1111” (44.1kHz)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKO1-0: BCLK Output Frequency Select at Master Mode (Table 10)
Default: “01” (32fs)
HPFA1-0: Offset Cancel HPF Cut-off Frequency and ADCA Initialization Cycle (Table 20, Table 37)
Default: “00” (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Addr
Register Name
D7
D6
06H
Clock Output Select
INCA
0
Default
0
0
INCA: ADCA Initialization Cycle (Table 37)
0: When HPFA1-0 bits = “00”, “01”, “10”, INCA bit is invalid, when HPFA1-0 bits = “11”, ADCA Initialization
Cycle becomes 3088/fs.
1: When HPFA1-0 bits = “00”, “01”, “10”, INCA bit is invalid, when HPFA1-0 bits = “11”, ADCA Initialization
Cycle becomes 1552/fs.
PS1-0: MCKO Output Frequency Select (Table 9)
Default: “00” (256fs)
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
D5
D4
D3
FS3
1
D2
FS2
1
D1
FS1
1
D0
FS0
1
BCKO1
0
BCKO0
1
D5
0
0
D4
0
0
D3
0
0
D2
D1
PS1
0
D0
PS0
0
MCKO
0
Addr
04H
Register Name
Audio Format Select
Default
D7
D6
D5
1
1
D4
MIXA
0
D3
MSBS
0
D2
BCKP
0
D1
DIF1
1
D0
DIF0
1
TDM1
0
TDM0
0
相關(guān)PDF資料
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