參數(shù)資料
型號(hào): AK5702VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 4-Channel ADC with PLL & MIC-AMP
中文描述: 4通道ADC,帶鎖相環(huán)
文件頁(yè)數(shù): 28/76頁(yè)
文件大小: 933K
代理商: AK5702VN
[AK5702]
MS0623-E-00
2007/06
- 28 -
EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
The AK5702 becomes EXT Master Mode by setting as Figure 63. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is
selected by FS3-0 bits (Table 12).
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Frequency
256fs
1024fs
512fs
256fs
N/A
Sampling Frequency
Range
7.35kHz
48kHz
7.35kHz
13kHz
7.35kHz
26kHz
7.35kHz
48kHz
-
0
1
2
3
4
00, 01, 11
00, 01, 11
00, 01, 11
00, 01, 11
10
0
0
1
1
0
1
0
1
(default)
Don’t care
Table 12. MCKI Frequency at EXT Master Mode
Don’t care
MCKI should always be present whenever the ADC is in operation (PMADAL bit = “1” or PMADAR bit = “1” or
PMADBL bit = “1” or PMADBR bit = “1”). If MCKI is not provided, the AK5702 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC should
be in the power-down mode (PMADAL= PMADAR = PMADBL = PMADBR bits = “0”).
AK5702
DSP or
μ
P
MCKI
BCLK
LRCK
SDTOA/B
BCLK
LRCK
SDTI
MCKO
1fs
32fs or 64fs
MCLK
256fs, 512fs or 1024fs
Figure 24. EXT Master Mode
BCKO1 bit
BCKO0 bit
BCLK Output
Frequency
N/A
32fs
64fs
N/A
0
0
1
1
Table 13. BCLK Output Frequency at Master Mode
0
1
0
1
(default)
相關(guān)PDF資料
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