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參數(shù)資料
| 型號： | AK5702VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 4-Channel ADC with PLL & MIC-AMP |
| 中文描述： | 4通道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 933K |
| 代理商： | AK5702VN |
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[AK5702]
MS0623-E-00
2007/06
- 22 -
OPERATION OVERVIEW
■
System Clock
There are the following five clock modes to interface with external devices (Table 1 and Table 2.)
Mode
PLL Master Mode (Note 27)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BCLK pin)
EXT Slave Mode
EXT Master Mode (Note 28)
Note 27. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Note 28. In case of EXT Master Mode, the register should be set as Figure 64.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
MCKO pin
0
PLL Master Mode
1
PS1-0 bits
0
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
PS1-0 bits
PLL Slave Mode 2
(PLL Reference Clock: LRCK
or BCLK pin)
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 20
1
0
See Table 4
Figure 21
1
0
See Table 4
Figure 22
0
0
0
1
x
x
Figure 23
Figure 24
MCKI pin
BCLK pin
BCLK pin
(Selected by
BCKO1-0 bits)
LRCK pin
“L”
Selected by
Selected by
PLL3-0 bits
LRCK pin
(1fs)
“L”
Selected by
Selected by
PLL3-0 bits
BCLK pin
(
≥
32fs)
LRCK pin
(1fs)
0
“L”
GND
BCLK pin
(Selected by
PLL3-0 bits)
BCLK pin
(
≥
32fs)
BCLK pin
(Selected by
BCKO1-0 bits)
LRCK pin
(1fs)
EXT Slave Mode
0
“L”
Selected by
FS1-0 bits
LRCK pin
(1fs)
EXT Master Mode
0
“L”
Selected by
FS1-0 bits
LRCK pin
(1fs)
Table 2. Clock pins state in Clock Mode
■
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK5702 is power-down mode (PDN pin = “L”) and exits reset state, the AK5702 is slave mode. After exiting reset state,
the AK5702 goes to master mode by changing M/S bit = “1”.
When the AK5702 is used by master mode, LRCK and BCLK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK5702 should be pulled-down or pulled-up by the resistor (about 100k
Ω
) externally to avoid the
floating state. When PDN pin is “H” and PMVCM bit becomes “L”, LRCK, BCLK pin output “L” or “H”. In this
situation, it is possible to draw the current into pulled-down or pulled-up resister. This current can stop by setting M/S bit
to “0”.
PDN pin
PMVCM bit
M/S bit
L
L
L
H
L
L
H
L
H
H
H
L
H
H
H
Table 3. Select Master/Salve Mode
Mode
Slave
Slave
Master
Slave
Master
LRCK,BCLK pin
Input
Input
Output “L” or “H”
Input
Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK6002A | Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No |
| AK6002AF | Circular Connector; No. of Contacts:23; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-99 RoHS Compliant: No |
| AK6002AV | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AK6004A | Circular Connector; No. of Contacts:26; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:16-26 RoHS Compliant: No |
| AK6004AF | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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