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參數(shù)資料
| 型號： | AK5702VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 4-Channel ADC with PLL & MIC-AMP |
| 中文描述： | 4通道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 50/76頁 |
| 文件大?。?/td> | 933K |
| 代理商： | AK5702VN |
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[AK5702]
MS0623-E-00
2007/06
- 50 -
(2) I
2
C-bus Control Mode (I2C pin = “H”)
The AK5702 supports the fast-mode I
2
C-bus (max: 400kHz).
(2)-1. WRITE Operations
Figure 47 shows the data transfer sequence for the I
2
C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 53). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0
(device address bit). This bit identifies the specific device on the bus. The hard-wired input pins (CAD1/0 pins) set these
device address bits (Figure 48). If the slave address matches that of the AK5702, the AK5702 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 54). A R/W bit value of “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5702. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 49). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 50). The AK5702 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 53).
The AK5702 can perform more than one byte write operation per sequence. After the receipt of the third byte the AK5702
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1CH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 55) except for the START and STOP
conditions.
SDA
Slave
Address
S
S
T
A
R
T
R/W="0"
A
C
K
Sub
Address(n)
A
C
K
Data(n)
A
C
K
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
S
T
O
P
Figure 47. Data Transfer Sequence at the I
2
C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 48. The First Byte
0
0
A5
A4
A3
A2
A1
A0
Figure 49. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 50. Byte Structure after the second byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK6002A | Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No |
| AK6002AF | Circular Connector; No. of Contacts:23; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-99 RoHS Compliant: No |
| AK6002AV | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AK6004A | Circular Connector; No. of Contacts:26; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:16-26 RoHS Compliant: No |
| AK6004AF | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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