參數(shù)資料
型號: AK4650VG
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
中文描述: 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 69/86頁
文件大?。?/td> 824K
代理商: AK4650VG
[AK4650]
MS0502-E-01
2007/04
- 69 -
Power On
Note that AK4650 must be in cold reset at power on and RESETN must be “L” until master crystal clock becomes stable,
or cold reset must be done once after master clock is stable.
BIT_CLK
Initialize Registers
start up crystal oscillation
SYNC=”L”
SDATA_OUT=”L”
RESETN
Vdd
T
rst2clk
Figure 53. Power On Timing
Cold Reset
Note that both SDATAOUT and SYNC must be “L” at the rising edge of RESETN for cold reset.
The AK4650 initializes all registers including the Power-down Control Registers, BIT-CLK is reactivated and each
analog output except for HP-Amp is in Hi-Z state while RESETN pin is “L”.
At the rising edge of RESETN, the AK4650 starts the initialization of ADC and DAC, which takes 1028TS cycles. After
that, the AK4650 is ready for normal operation. At that time, VRA bit is its default value (“0”). Therefore, fs=48kHz and
TS=1/fs=20.83
μ
s.
Status bit in the slot 0 is “0” (not ready) when the AK4650 is in RESET period (“L”) or in initialization process. After
initialization cycles, the status bit goes to “1” (ready).
Trst_low
BIT_CLK
VIL
RESETN
Trst2clk
SYNC= “L”
SDATA_OUT= “L”
Figure 54. Cold Reset Timing
相關(guān)PDF資料
PDF描述
AK4651 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4651VG 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4665A 20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 20-Bit Stereo CODEC with MIC/HP-AMP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AK4665A 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP