- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385094 > AK4650VG (Asahi Kasei Microsystems Co.,Ltd) 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC PDF資料下載
參數(shù)資料
| 型號(hào)： | AK4650VG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| 中文描述： | 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁(yè)數(shù)： | 31/86頁(yè) |
| 文件大?。?/td> | 824K |
| 代理商： | AK4650VG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)當(dāng)前第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)
[AK4650]
MS0502-E-01
2007/04
- 31 -
(3)
Example of ALC1 Operation
Table 22 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
Register
Name
LMTH
Limiter detection Level
LTM1-0
Limiter operation period at ZELMN
bit = “1”
ZELMN
Limiter zero crossing detection
ZTM1-0
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same
data as ZTM1-0 bits
REF5-0
Maximum gain at recovery operation
IPGA5-0
Gain of IPGA at ALC1 operation start
LMAT1-0
Limiter ATT Step
RGAIN
Recovery GAIN Step
ALC1
ALC1 Enable bit
Table 22. Example of the ALC1 setting
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN, REF5-0, ZELMN bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA5-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
fs=8kHz
Operation
4dBFS
Don’t use
fs=16kHz
Operation
4dBFS
Don’t use
fs=44.1kHz
Data
1
00
Comment
Data
1
00
Data
1
00
Operation
4dBFS
Don’t use
0
00
Enable
16ms
0
01
Enable
16ms
0
10
Enable
11.6ms
WTM1-0
00
16ms
01
16ms
10
11.6ms
3DH
37H
00
0
1
+26.5dB
0dB
0.5dB
0.5dB
Enable
3DH
37H
00
0
1
+26.5dB
0dB
0.5dB
0.5dB
Enable
3DH
37H
00
0
1
+26.5dB
0dB
0.5dB
0.5dB
Enable
Manual Mode
* The value of IPGA should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF5-0)
WR (IPGA5-0)
ALC1 Operation
Note : WR : Write
WR (ALC1= “1”, LMAT1-0, RGAIN, LMTH, ZELMN)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 0.5dB
Maximum Gain = +26.5dB
Limiter Detection Level =
4dBFS
ALC bit = “1”
(1) Addr=66H, Data=4100H
(2) Addr=64H, Data=3D31H
(4) Addr=66H, Data=6100H
(3) Addr=0EH, Data=0077H
Figure 19. Registers set-up sequence at ALC1 operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4651 | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4651VG | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4665A | 20-Bit Stereo CODEC with MIC/HP-AMP |
| AK4665AEN | 20-Bit Stereo CODEC with MIC/HP-AMP |
| AK4671 | Stereo CODEC with MIC/RCV/HP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4651 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4651VG | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4664VQ | 功能描述:IC CODEC STEREO 20BIT LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購(gòu)買(mǎi)時(shí)間 標(biāo)準(zhǔn)包裝:1,000 |
| AK4665A | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP |
| AK4665AEN | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。