參數(shù)資料
型號: AK4650VG
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
中文描述: 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 22/86頁
文件大?。?/td> 824K
代理商: AK4650VG
[AK4650]
MS0502-E-01
2007/04
- 22 -
System Clock
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 pins (Table 2).
When the external master clock is used, the PLL should be powered-up after the external master clock is input. It takes
0.5ms(typ) for X’tal oscillator to be stable after PR5 bit = “0” which depends on the X’tal. The PLL needs 9ms lock time,
whenever the sampling frequency changes or the PLL is powered-up (VRA bit = “0”
“1”).
When the clock input to MCKI pin stops during normal operation of AC-Link (PR4 = PR5 bits = “0”), the internal PLL
continues to oscillate (a few MHz), and BITCLK output goes to “L” (Table 3).
MCLK and SYNC must be present whenever the ADC or DAC is operating (PR0 = PR1 = PR3 = PR4 = PR5 bits = “0”).
If these clocks are not provided, the AK4650 may draw excess current due to its use of internal dynamically refreshed
logic. If the external clocks are not present, the ADC and DAC must be placed in the power-down mode by setting PR0-6
bits.
PLL1 pin
PLL0 pin
L
L
H
L
H
H
Table 2. MCKI Input Frequency
Power up
Frequency set by PLL1-0
pins (Table 2)
BITCLK pin
12.288MHz Output
MCKI
24.576MHz
N/A
3.6864MHz
12MHz
Power down
PLL Unlock
MCKI pin
Refer to Table 1
Frequency set by PLL1-0 pins
(Table 2)
“L”
Input
or
Fixed to “L” or “H” externally
“L”
SYNC pin
Input
Fixed to “L” or “H” externally
Table 3. Clock Operation
相關(guān)PDF資料
PDF描述
AK4651 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4651VG 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4665A 20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 20-Bit Stereo CODEC with MIC/HP-AMP
AK4671 Stereo CODEC with MIC/RCV/HP-AMP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AK4665A 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP