參數(shù)資料
型號： AK4650VG
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
中文描述： 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù)： 67/86頁
文件大小： 824K
代理商： AK4650VG
[AK4650]
MS0502-E-01
2007/04
- 67 -
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of
BITCLK. On the immediately following falling edge of BITCLK, the AK4650 samples the assertion of SYNC. This
falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of
BITCLK, the AK4650 transitions SDATAIN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit
position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the AC ’97 controller on the
following falling edge of BITCLK. This sequence ensures that data transitions, and subsequent sample points for both
incoming and outgoing data streams are time aligned.
SYNC
“0”
Bit4
“1/0”
“1/0”
Slot6
Slot7
Slot5
Slot4
Slot3
Slot2
Slot1
Codec
Ready
“1/0”
Bit15 Bit14 Bit13 Bit12 Bit11
Slot 1
Slot 0
SDATAIN
BITCLK
“1/0” “1/0”
“0”
Bit8
“1/0”
Bit9
“1/0”
Bit10
Slot12
“0”
Bit0
“0”
Bit1
“0”
Bit2
“1/0”
Bit3
Slot8
Slot11
“0”
Bit7
Figure 51. Slot 0
[Slot 1]: Status Address Port
Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in
slot 2. (Assuming that slot 1 valid bit and slot 2 valid bit in the slot 0 had been tagged “valid” by the AK4650.)
BITCLK
Bit15
“1/0”
“1/0”
Bit14
Bit16
Bit17
Bit18
Bit19
Status Address Port
Slot 2
Slot 0
Slot 1
SDATAIN
“1/0” “1/0”
“0”
“0”
“1/0”
“0”
“1/0”
Bit8
Bit9
Bit10
Bit12
Bit11
Bit13
“1/0” “1/0” “1/0”
“0”
Bit7
“0”
“0”
Bit1
Bit5
Bit6
Bit2
Bit3
Bit4
Bit0 Bit19
“0”
“0”
“0”
“0”
“0”
Figure 52. Slot 1
This address shows register index for which data is being returned in the slot 2. This address port is the copy of slot 1 of
the output frame, and index address input to SDATAOUT is looped back to the AC’97 controller through SDATAIN
even for non-supported register.
For “On Demand” base data transaction, when the DAC sampling rate is set less than 48kHz, then AK4650 will request
new audio data as required by setting the SLOTREQ bits 11 and 10 in slot 1 to 0’s. When no data is required to support the
selected sampling rate, these bits will be 1’s. When SLOTREQ bits are asserted as “send data request” during the current
frame on SDATAIN, AC’97 digital controller should send data onto the corresponding slot in the next frame on
SDATAOUT. If VRA bit is set to “0”, SLOTREQ bits always show “0” and sample rate is tired to 48kHz.
SLOTREQ Bit Description
19
Reserved (Set to “0”)
18-12
Control Register Index (7bit; Set to “0” if tagged invalid)
11
Slot 3 Request: PCM Lch
“0”: send data request, “1”: do not send
10
Slot 4 Request: PCM Rch
“0”: send data request, “1”: do not send
9-0
Reserved (10bit; Set to “0”)
Table 56. SLOTREQ bit
相關(guān)PDF資料
PDF描述
AK4651 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4651VG 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4665A 20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 20-Bit Stereo CODEC with MIC/HP-AMP
AK4671 Stereo CODEC with MIC/RCV/HP-AMP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4651 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4651VG 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4664VQ 功能描述:IC CODEC STEREO 20BIT LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時(shí)間 標(biāo)準(zhǔn)包裝:1,000
AK4665A 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*