參數(shù)資料
型號: AK4650VG
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
中文描述: 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 62/86頁
文件大小: 824K
代理商: AK4650VG
[AK4650]
MS0502-E-01
2007/04
- 62 -
SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio
frame where SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is
defined as the “Data Phase”.
Note that SDATAOUT and SDATAIN data is delayed one BITCLK because AC’97 controller causes
SYNC signal high at a rising edge of BITCLK which initiates a frame.
“Output” stream means the direction from AC’97 controller to the AK4650, and “Input” stream means the direction from
the AK4650 to AC’97 controller.
AC-Link Protocol
12
11
10
9
8
7
6
5
4
3
2
1
48kHz
Data Phase
Tag Phase
Slot
0
SYNC
All
“0”
All
“0”
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
PCM(dac)
Right
PCM(dac)
Left
Command
Data
Command
Address
TAG
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
All
”0”
12bit ADC
Data
12bit ADC
Data
All
”0”
PCM(adc)
Left
Status
Data
Status
Address
SDATA
IN
TAG
12bit ADC
Data
SDATA
OUT
Figure 47. AC-Link protocol
AC-link protocol identifies 13 slots of data per frame. The frequency of SYNC is fixed to 48kHz. Only Slot 0, which is the
Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
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