參數(shù)資料
型號(hào)： AK4566VN
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 20bit Stereo CODEC with built-in IPGA & HP-AMP
中文描述： 20位立體聲編解碼器內(nèi)置單親遺傳算法
文件頁(yè)數(shù)： 39/45頁(yè)
文件大?。?/td> 454K
代理商： AK4566VN
ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
REV 0.5
2002/2
- 39 -
1. Grounding and Power Supply Decoupling
The AK4566 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the
analog power supply in the system and DVDD is supplied from AVDD via a 10
resistor. Alternatively if AVDD, DVDD
and HVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and HVSS must be connected to
the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies
are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4566 as possible, with the
small value ceramic capacitors being the nearest.
2. Internal Voltage Reference
Internal voltage reference is output on the VREF pin (typ. 2.1V). An electrolytic capacitor 4.7
μ
F in parallel with a 0.1
μ
F
ceramic capacitor is attached between VREF and AVSS to eliminate the effects of high frequency noise. VCOM is
1.25V(typ) and is a signal ground of this chip. A 2.2
μ
F electrolytic capacitor in parallel with a 0.1
μ
F ceramic capacitor
should be connected between VCOM and AVSS to eliminate the effects of high frequency noise. A ceramic capacitor
should be connected to VCOM pin and located as close as possible to the AK4566. No load current may be drawn from
VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to
avoid unwanted coupling into the AK4566.
3. Analog Inputs
The analog inputs are single-ended and the input resistance 50k
(typ) for AINL1/AINR1 pins and 12.5k
(typ) for
AINL2/AINR2 pins. The input signal range is 1.5Vpp centered around VCOM voltage. Usually, the input signal cuts DC
with a capacitor. The cut-off frequency is fc=(1/2
π
RC). The AK4566 can accept input voltages from AVSS to AVDD. The
ADC output data format is 2’s complement. The DC offset including ADC own DC offset is removed by the internal HPF
(fc=3.4Hz@fs=44.1kHz).
4. Analog Outputs
The analog outputs are single-ended outputs and 1.5Vpp(typ) centered around the VCOM voltage. The input data format
is 2’s compliment. The output voltage is a positive full scale for 7FFFFH(@20bit) and negative full scale for
80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). If the noise generated by the delta-sigma
modulator beyond the audio band causes problems, attenuation by an external filter is required.
DC offsets on the analog outputs is eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few
mV.
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