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參數(shù)資料
| 型號(hào)： | AK4566VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| 中文描述： | 20位立體聲編解碼器內(nèi)置單親遺傳算法 |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 454K |
| 代理商： | AK4566VN |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
REV 0.5
2002/2
- 19 -
n
IPGA Operation
[Write Operation at ALC Enabled]
The values of IPGA6-0 bits are ignored during ALC operation.
[Write Operation at ALC Disabled]
Channel independent zero crossing detection is used. If there is no zero crossings, then the level will change after a timeout.
The ZTM1-0 bits set the zero crossing timeout. When the IPGA7-0 bits are written by
μ
P, the zero crossing counter is reset
and starts. When the IPGA output signal detects zero crossing or zero crossing timeout, the written value by
μ
P becomes
valid.
When writing to the IPGA7-0 bits continually, the control register should be written by an interval more
than zero crossing timeout.
If not, there is a possibility that each IPGA of L/R channels has a different gain.
[IPGA Gain after completing ALC operation]
The IPGA7-0 bits are not updated by the actual gain of IPGA changed during ALC operation. In order to set the actual gain
of IPGA with the IPGA7-0 bits, the IPGA7-0 bits should be written after zero crossing timeout period when completing
ALC operation (ALC bit= “1”
à
“0”).
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