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參數(shù)資料
| 型號(hào)： | AK4566VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| 中文描述： | 20位立體聲編解碼器內(nèi)置單親遺傳算法 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 454K |
| 代理商： | AK4566VN |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
REV 0.5
2002/2
- 14 -
OPERATION OVERVIEW
n
System Clock
The external clocks required to operate the AK4566 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The
frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 1
shows system clock example.
LRCK
MCLK (MHz)
fs
256fs
384fs
8kHz
2.048
3.072
11.025kHz
2.8224
4.2336
12kHz
3.072
4.608
16kHz
4.096
6.144
22.05kHz
5.6448
8.4672
24kHz
6.144
9.216
32kHz
8.192
12.288
44.1kHz
11.2896
16.9344
48kHz
12.288
18.432
Table 1. System Clock Example
All external clocks (MCLK, BICK and LRCK) should always be present whenever the ADC or DAC is in normal
operation mode (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4566 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external
clocks are not present, ADC and DAC should be placed in the power-down mode (PMADC bit = PMDAC bit = “0”).
When MCLK is input with AC coupling, MCKAC bit should be set to “1”. When MCLK with AC coupling stops, MCKPD
bit should be set to “1”.
When low sampling rate, DR and S/N degrade because of the outband noise. DR and S/N are approved by setting DFS bit
to “1”. Table 2 shows S/N in the case DAC output to HP-amp and MOUT. When DFS bit is “1”, MCLK needs 512fs.
When sampling frequency is changed at normal operation mode of ADC or DAC (PMADC bit = “1” or PMDAC bit = “1”),
DAC output should be soft-muted or “0” data should be input to avoid click noise.
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
512fs
4.096
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
S/N (fs=8kHz, A-weighted)
HP-amp
84dB
90dB
Default
DFS
fs
MCLK
MOUT
84dB
88dB
0
1
8kHz
～
48kHz
8kHz
～
24kHz
256fs/384fs/512fs
512fs
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
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