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參數(shù)資料
| 型號(hào)： | AK4566VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| 中文描述： | 20位立體聲編解碼器內(nèi)置單親遺傳算法 |
| 文件頁數(shù)： | 22/45頁 |
| 文件大?。?/td> | 454K |
| 代理商： | AK4566VN |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
REV 0.5
2002/2
- 22 -
n
Power-Up/Down Sequence
1) ADC
Power Supply
PDN pin
PMVCM bit
Clock Input
PMADC bit
ADC Internal
State
AIN pin
PD(Power-down) Init Cycle
Normal Operation
(6) 2081/fs
SDTO pin
(7) GD
(5)
(4)
PD
Normal Operation
Init Cycle
(7) GD
(6) 2081/fs
(7) GD
(Hi-Z)
(Hi-Z)
Don’t care
Don’t care
Don’t care
HPLMT,
HPRMT bit
(1) >150ns
(2)
>0
(3) >0
Figure 17. Power-up/down sequence of ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMADC bit should be changed to “1” after HPLMT, HPRMT and PMVCM bits are changed to “1”.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate ADC. When PMADC= “0”, these clocks can be
stopped.
(5) When PMADC bit is changed to “1”, each AIN pin is biased to VCOM voltage. Rising time constant is determined by
input capacitor for AC coupling and input resistance. In case of AINL2/AINR2 and 1μF input capacitor, time constant
is
τ
= 1μF x 12.5k
= 12.5ms (typ)
(6) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state. SDTO
is “L” at that time.
(7) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385μs@fs=44.1kHz).
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