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參數(shù)資料
| 型號： | AK4566VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| 中文描述： | 20位立體聲編解碼器內(nèi)置單親遺傳算法 |
| 文件頁數(shù)： | 24/45頁 |
| 文件大?。?/td> | 454K |
| 代理商： | AK4566VN |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
REV 0.5
2002/2
- 24 -
3) DAC
→
MOUT
Power Supply
PDN pin
PMVCM bit
Clock Input
(4)
SDTI pin
PMDAC bit
DAC Internal
State
PD(Power-down)
Normal Operation
PMMO bit
ATTL/R7-0 bit
00H(MUTE)
FFH(0dB)
MOUT pin
(5)
MMUTE,
ATTM3-0 bit
10H(MUTE)
0FH(0dB)
(6) GD
(7) 1061/fs
(Hi-Z)
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(Hi-Z)
(6)
(7)
(5)
(5)
(6) (7)
Don’t care
Don’t care
HPLMT,
HPRMT bit
Don’t care
(1) >150ns
(2)
>0
(3) >0
Figure 19. Power-up/down sequence of DAC and MOUT
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMDAC and PMMO bits should be changed to “1” after HPLMT, HPRMT and PMVCM bits are changed to “1”.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC= “0”, these clocks can be
stopped. MOUT buffer can operate without these clocks.
(5) When PMMO bit is changed to “1”, click noise is output from MOUT pin.
(6) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381μs@fs=44.1kHz).
(7) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
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