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參數(shù)資料
| 型號： | AK4565 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | LOW POWER 20BIT CODEC WITH BUILT IN ALC |
| 中文描述： | 低功耗20位編解碼器中的ALC的建造 |
| 文件頁數(shù)： | 19/33頁 |
| 文件大小： | 249K |
| 代理商： | AK4565 |
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ASAHI KASEI
[AK4565]
MS0132-E-01
2003/05
- 19 -
n
Operation of IPGA
[Writing operation at ALC Enable]
Writing to IPGA6-0 bit is ignored during ALC operation and FADEIN/OUT operation.
[Writing operation at ALC Disable]
When writing to the control register continually, the control register should be written by an interval
more than zero crossing timeout.
If not, there is a possibility that each IPGA of L/R channels has a different gain.
[IPGA Gain after completing ALC operation]
The IPGA gain changed by ALC operation. The actual gain of IPGA is changed during ALC operation but the IPGA
register doesn’t change. Therefore, when completing ALC operation (ALC bit; “1”
à
“0”), the IPGA register is different
from the actual gain of IPGA. The value should be written to the IPGA register in order to set the actual gain of IPGA
with a register value.
[Operation of IPGA at power-down by the control register]
IPGA gain is reset when PM0 bit is “0”, and then IPGA operation starts from the default value when PM0 bit is changed
to “1”. When IPGA6-0 bits are read, the register values written by the last write operation are read out regardless the
actual gain.
n
Control Register R/W Timing
The data on the 4 wires serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,
8bit). The transmitting data is output to each bit by “
↓
” of CCLK, the receiving data is latched by “
↑
” of CCLK. Writing
data becomes effective by “
↑
” of CSN. Reading data becomes Hi-z (Floating) by “
↑
” of CSN. CSN should be held to “H”
at no access. In case of connecting between CDTI and CDTO, the I/F can be also contolled by 3-wires.
CCLK always needs 16 edges of “
-
” during CSN = “L”. Reading/Writing of the address except 00H
~
09H are inhibited. Reading/Writing of the control registers by except op0 = op1 = “1” are invalid.
WRITE
READ
Hi-Z
Hi-Z
CSN
CCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15
CDTI
CDTO
Hi-Z
CDTI
CDTO
op1
“1”
op0
“1”
op0
“1”
op1
“1”
op2
“0”
A2
A2
A1
A1
A3
A3 A4
A4
A0
A0
D0
D0 D1
D1 D2
D2
D3
D3 D4
D4 D5
D5 D6
D6
D7
D7
op2
“1”
op0-op2: Op code (110:READ, 111:WRITE)
A0-A4:
Register Address
D0-D7:
Control data
Figure 16. Control Data Timing
相關PDF資料 |
PDF描述 |
|---|---|
| AK4565VF | LOW POWER 20BIT CODEC WITH BUILT IN ALC |
| AK4566 | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4566VN | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4569 | 20-Bit Stereo CODEC with IPGA & HP-AMP |
| AK4569VN | 20-Bit Stereo CODEC with IPGA & HP-AMP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4565VF | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 20BIT CODEC WITH BUILT IN ALC |
| AK4566 | 制造商:AKM 制造商全稱:AKM 功能描述:20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4566VN | 制造商:AKM 制造商全稱:AKM 功能描述:20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4568AER | 功能描述:IC CODEC LOW POWER 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標準包裝:1,000 |
| AK4569 | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with IPGA & HP-AMP |
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