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參數(shù)資料
| 型號： | AK4565 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | LOW POWER 20BIT CODEC WITH BUILT IN ALC |
| 中文描述： | 低功耗20位編解碼器中的ALC的建造 |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AK4565 |
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ASAHI KASEI
[AK4565]
MS0132-E-01
2003/05
- 18 -
n
FADEOUT Mode
In FADEOUT mode, the present IPGA value decreases gradually down to the MUTE state when FDOUT bit changes from
“0” to “1”. This operation is done by the zero crossing detection. If the large signal is supplied to the ALC circuit during the
FADEOUT operation, the ALC limiter operation starts. However, the total time of the FADEOUT operation is the same
time, even if the limiter operation is done. The period of FADEOUT is set by FDTM1-0 bits, the number of step is set by
FDATT bit. When FDOUT bit changes into “0” during the FADEOUT operation, the ALC operation start from the preset
IPGA value. When FDOUT and ALC bits change into “0” at the same time, the FADEOUT operation stops and the IPGA
kept the value at that time.
NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation.
IPGA Output
ALC bit
FDOUT bit
(1)
(5)
(6)
(7)
(4)
(3)
(2)
(8)
Figure 15. Example for controlling sequence in FADEOUT operation
(1) WR (FDOUT = “1”): The FADEOUT operation starts. Then ALC bit should be always “1”.
(2) FADEOUT time is set by FDTM1-0 and FDATT bits.
During the FADEIN operation, the zero crossing timeout period is ignored and becomes the same as the FADEIN
period.
E.g. FDTM1-0 = 32ms, FDATT = 1step
(96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s
(3) The FADEOUT operation is completed. The IPGA value is the MUTE state. If FDOUT bit keeps “1”, the IPGA value
keeps the MUTE state.
(4) Analog and digital outputs mutes externally. Then the IPGA value is the MUTE state.
(5) WR (ALC = FDOUT = “0”): Exit the ALC and FADEOUT operations
(6) WR (IPGA): The IPGA value changes the initial value (exiting MUTE state).
(7) WR (ALC = “1”, FDOUT = “0”): The ALC operation restarts. But the ALC bit should be written until completing zero
crossing detection operation of IPGA.
(8) Release an external mute function for analog and digital outputs.
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| AK4566 | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4566VN | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4569 | 20-Bit Stereo CODEC with IPGA & HP-AMP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4565VF | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 20BIT CODEC WITH BUILT IN ALC |
| AK4566 | 制造商:AKM 制造商全稱:AKM 功能描述:20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4566VN | 制造商:AKM 制造商全稱:AKM 功能描述:20bit Stereo CODEC with built-in IPGA & HP-AMP |
| AK4568AER | 功能描述:IC CODEC LOW POWER 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時(shí)間 標(biāo)準(zhǔn)包裝:1,000 |
| AK4569 | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with IPGA & HP-AMP |
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