參數(shù)資料
型號(hào)： AK4565
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： LOW POWER 20BIT CODEC WITH BUILT IN ALC
中文描述： 低功耗20位編解碼器中的ALC的建造
文件頁數(shù)： 17/33頁
文件大?。?/td> 249K
代理商： AK4565
ASAHI KASEI
[AK4565]
MS0132-E-01
2003/05
- 17 -
n
FADEIN Mode
In FADEIN Mode, the IPGA value increases gradually by the step set by FDATT bit when FDIN bit changes from “0” to
“1”. The FADEIN period is set by FDTM1-0 bits. The FADEIN operation is done by the zero crossing detection. This
operation stops when the IPGA value becomes the REF value or the limiter detection level (LMTH). If the limiter
operation is done during FADAIN period, the FADEIN operation stops and the ALC operation starts.
NOTE: When FDIN and FDOUT bits are “1”at the same time, FADEOUT operation is prior to FADEIN operation.
IPGA Output
ALC bit
FDIN bit
(1) (2)
(3)
(4)
(5)
Figure 14. Example for controlling sequence in FADEIN operation
(1) WR (ALC = FDIN = “0”): The ALC operation is disabled. To start the FADEIN operation, FDIN bit is written in “0”.
(2) WR (IPGA = “MUTE”): The IPGA output is muted.
(3) WR (ALC = FDIN = “1”): The FADEIN operation starts. The IPGA changes from the MUTE state to the FADEIN
operation.
(4) The FADEIN operation is done until the limiter detection level (LMTH) or the reference level (REF6-0). After
completing the FADEIN operation, the AK4565 becomes the ALC operation.
(5) FADEIN time is set by FDTM1-0 and FDATT bits
E.g. FDTM1-0 = 32ms, FDATT = 1step
(96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s
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AK4569 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with IPGA & HP-AMP
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