參數(shù)資料
型號(hào): ADV7343BSTZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 72/108頁(yè)
文件大?。?/td> 0K
描述: IC ENCODER VIDEO W/DAC 64-LQFP
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: DVD,Blu-Ray
電壓 - 電源,模擬: 3.3V
電壓 - 電源,數(shù)字: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
ADV7342/ADV7343
Data Sheet
Rev. | Page 66 of 108
O XXXXXXO O XXXXXXO
DNR27 TO DNR24 = 0x01
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
APPLY BORDER
CORING GAIN
APPLY DATA
CORING GAIN
06399-
079
Figure 75. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
720 × 485 PIXELS
(NTSC)
8 × 8 PIXEL BLOCK
TWO-PIXEL
BORDER
DATA
8 × 8 PIXEL BLOCK
06399-
080
Figure 76. SD DNR Border Area
Block Size Control—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.
FILTER C
FILTER B
FILTER A
FILTER D
FREQUENCY (MHz)
0
0.2
0.4
0.6
M
AG
NI
T
UDE
0.8
1.0
0
1
2
3
4
5
6
06399-
081
Figure 77. SD DNR Input Select
DNR Input Select Control—Subaddress 0xA5, Bits[2:0]
Three bits are assigned to select the filter, which is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that is DNR processed. Figure 77
shows the filter responses selectable with this control.
DNR Mode Control—Subaddress 0xA5, Bit 3
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
DNR Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
The ADV7342/ADV7343 are able to control fast rising and
falling signals at the start and end of active video in order to
minimize ringing.
When the active video edge control feature is enabled
(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last
three pixels of the active video on the luma channel are scaled
so that maximum transitions on these pixels are not possible.
At the start of active video, the first three pixels are multiplied by
1/8, 1/2, and 7/8, respectively. Approaching the end of active video,
the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively.
All other active video pixels pass through unprocessed.
D
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