參數(shù)資料
型號(hào)： ADV7343BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/108頁(yè)
文件大小： 0K
描述： IC ENCODER VIDEO W/DAC 64-LQFP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： DVD，Blu-Ray
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
ADV7342/ADV7343
Data Sheet
Rev.
| Page 30 of 108
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7342/ADV7343 via the MPU port, except for registers that
are specified as read-only or write-only registers.
The subaddress register determines which register the next
read or write operation accesses. All communication through
the MPU port starts with an access to the subaddress register.
A read/write operation is then performed from/to the target
address, which increments to the next address until the
transaction is complete.
REGISTER PROGRAMMING
Table 17 to Table 35 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines to or
from which register the operation takes place.
Table 17. Register 0x00
SR7 to
Bit Number
Register
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Setting
Value
0x00
Power
mode
Sleep mode. With this control enabled, the current consumption is
reduced to μA level. All DACs and the internal PLL circuits are
disabled. Registers can be read from and written to in sleep mode.
0
Sleep
mode off
0x12
1
Sleep
mode on
PLL and oversampling control. This control allows the internal PLL 1
circuit to be powered down and the oversampling to be switched off.
0
PLL 1 on
1
PLL 1 off
DAC 3: power on/off.
0
DAC 3 off
1
DAC 3 on
DAC 2: power on/off.
0
DAC 2 off
1
DAC 2 on
DAC 1: power on/off.
0
DAC 1 off
1
DAC 1 on
DAC 6: power on/off.
0
DAC 6 off
1
DAC 6 on
DAC 5: power on/off.
0
DAC 5 off
1
DAC 5 on
DAC 4: power on/off.
0
DAC 4 off
1
DAC 4 on
Table 18. Register 0x01 to Register 0x09
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x01
Mode select
Reserved.
0
0x00
DDR clock edge alignment
(only used for ED-2 and
HD-DDR modes)
0
Chroma clocked in on rising clock edge; luma
clocked in on falling clock edge
0
1
Reserved
1
0
Reserved
1
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge
Reserved.
0
Input mode (see Register
0x30, Bits[7:3] for ED/HD
standard selection)
0
SD input only
0
1
ED/HD-SDR input only
0
1
0
ED/HD-DDR input only
0
1
SD and ED/HD-SDR
1
0
SD and ED/HD-DDR
1
0
1
Reserved
1
0
Reserved
1
ED only (at 54 MHz)
Y/C/S bus swap
0
Allows data to be applied to data ports in
various configurations (SD feature only)
1
D
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